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AM85C30-8JC データシート(PDF) 10 Page - Advanced Micro Devices |
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AM85C30-8JC データシート(HTML) 10 Page - Advanced Micro Devices |
10 / 68 page AMD 10 Am85C30 Data Path The transmit and receive data path illustrated in Figure 2 is identical for both channels. The receiver has three 8-bit buffer registers in a FIFO arrangement, in addition to the 8-bit receive shift register. This scheme creates additional time for the CPU to service an interrupt at the beginning of a block of high-speed data. Incoming data are routed through one of several paths (data or CRC) depending on the selected mode (the character length in asynchronous modes also determines the data path). The transmitter has an 8-bit transmit data buffer register loaded from the internal data bus and a 20-bit transmit shift register that can be loaded either from the sync- character registers or from the transmit data register. Depending on the operational mode, outgoing data are routed through one of four main paths before they are transmitted from the Transmit Data output (TxD). Table 1. Read and Write Register Functions Write Register Functions RR0 Transmit/Receive buffer status and External status RR1 Special Receive Condition status (also 10 × 19 bit FIFO Frame Reception Status if WR15 bit D2 is set) RR2 Modified interrupt vector (Channel B only) Unmodified interrupt vector (Channel A only) RR3 Interrupt Pending bits (Channel A only) RR6 LSB Byte Count (14-bit counter) (if WR15 bit D2 set) RR7 MSB Byte Count (14-bit counter) and 10 × 19 bit FIFO Status (if WR15 bit D 2 is set) RR8 Receive buffer RR10 Miscellaneous XMTR, RCVR status RR12 Lower byte of baud rate generator time constant RR13 Upper byte of baud rate generator time constant RR15 External/Status interrupt information WR0 Command Register, Register Pointers CRC initialize, initialization commands for the various modes, shift right/shift left command WR1 Interrupt conditions and data transfer mode definition WR2 Interrupt vector (accessed through either channel) WR3 Receive parameters and control WR4 Transmit/Receive miscellaneous parameters and modes WR5 Transmit parameters and controls WR6 Sync character or SDLC address field WR7 Sync character or SDLC flag WR7 ′ SDLC/HDLC enhancements (if bit D0 of WR15 is set) WR8 Transmit buffer WR9 Master interrupt control and reset (accessed through either channel) WR10 Miscellaneous transmitter/receiver control bits, data encoding WR11 Clock mode control, Rx and Tx clock source WR12 Lower byte of baud rate generator time constant WR13 Upper byte of baud rate generator time constant WR14 Miscellaneous control bits, DPLL control WR15 External/Status interrupt control Read Register Functions Write Register Functions |
同様の部品番号 - AM85C30-8JC |
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同様の説明 - AM85C30-8JC |
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