74HC4516 datasheet(11/14 Pages) PHILIPS

11 / 14 page

December 1990

11

Philips Semiconductors

Product speciﬁcation

Binary up/down counter

74HC/HCT4516

AC WAVEFORMS

Fig.7

Waveforms showing the clock (CP) to

output (Qn) and terminal count (TC)

propagation delays, the clock pulse width

and the maximum clock pulse frequency.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.8

Waveforms showing the set-up and hold

times form count enable (CE) and up/down

(UP/DN) control inputs to the clock pulse

(CP), the propagation delays from UP/DN,

CE to TC.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.9

Waveforms showing the preset enable

pulse width, preset enable to output

delays and output transition times.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the master reset pulse,

master reset to terminal count and Qn

delay and master reset to clock removal

time.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

同様の部品番号 - 74HC4516

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