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74HC4510DB データシート(PDF) 9 Page - NXP Semiconductors |
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74HC4510DB データシート(HTML) 9 Page - NXP Semiconductors |
9 / 12 page December 1990 9 Philips Semiconductors Product specification BCD up/down counter 74HC/HCT4510 trem removal time MR to CP 23 13 29 35 ns 4.5 Fig.10 trem removal time PL to CP 17 10 21 26 ns 4.5 Fig.10 tsu set-up time UP/DN to CP 20 12 25 30 ns 4.5 Fig.8 tsu set-up time CE to CP 20 6 25 30 ns 4.5 Fig.8 tsu set-up time Dn to PL 20 6 25 30 ns 4.5 Fig.11 th hold time CE to CP 5 0 5 5 ns 4.5 Fig.8 th hold time Dn to PL 5 0 5 5 ns 4.5 Fig.11 th hold time UP/DN to CP 0 −5 0 0 ns 4.5 Fig.8 fmax maximum clock pulse frequency 30 53 24 20 MHz 4.5 Fig.7 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. max. AC WAVEFORMS Fig.7 Waveforms showing the clock (CP) to output (Qn) and terminal count (TC) propagation delays, the clock pulse width and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the set-up and hold times from count enable (CE) and up/down (UP/DN) control inputs to the clock pulse (CP), the propagation delays from UP/DN, CE to TC. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
同様の部品番号 - 74HC4510DB |
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同様の説明 - 74HC4510DB |
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