74HCT597 datasheet(2/12 Pages) PHILIPS

部品番号	74HCT597

部品情報	8-bit shift register with input flip-flops

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メーカー	PHILIPS [NXP Semiconductors]

ホームページ	http://www.nxp.com

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December 1990

2

Philips Semiconductors

Product speciﬁcation

8-bit shift register with input ﬂip-ﬂops

74HC/HCT597

FEATURES

• 8-bit parallel storage register inputs

• Shift register has direct overriding load and clear

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT597 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT597 consist each of an 8-bit storage

register feeding a parallel-in, serial-out 8-bit shift register.

Both the storage register and the shift register have

positive edge-triggered clocks. The shift register also has

direct load (from storage) and clear inputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC =5V

SHCP to Q

17

20

ns

STCP to Q

25

29

ns

PL to Q

21

26

ns

fmax

maximum clock frequency SHCP

96

83

MHz

CI

input capacitance

3.5

pF

CPD

power dissipation capacitance per package

notes 1 and 2

29

32

pF

同様の部品番号 - 74HCT597

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Nexperia B.V. All right...	74HCT597	314Kb / 20P	8-bit shift register with input flip-flops Rev. 5 - 26 October 2021
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	74HCT597D-Q100	298Kb / 19P	8-bit shift register with input flip-flops Rev. 2 - 26 October 2021

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同様の説明 - 74HCT597

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