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74LV374D データシート(PDF) 7 Page - NXP Semiconductors

部品番号 74LV374D
部品情報  Octal D-type flip-flop; positive edge-trigger 3-State
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メーカー  PHILIPS [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV374D データシート(HTML) 7 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
7
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V v 3.6V
VM = 0.5V * VCC at VCC t 2.7V and w 4.5V
VOL and VOH are the typical output voltage drop that occur with the
output load.
tPLH
tPHL
SV00343
CP INPUT
Qn OUTPUT
1/fmax
VM
tW
90%
VM
10%
tTHL
tTLH
Figure 1. Waveforms showing the clock (CP) to output (Qn)
propagation delays, the clock pulse width, output transition
times and the maximum clock pulse frequency
outputs
disabled
SV00344
VI
OE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
VM
tPLZ
tPHZ
tPZL
VY
outputs
enabled
outputs
enabled
VX
VM
tPZH
VM
Figure 2. Waveforms showing the 3-state enable and disable
times
t
su
t
su
SV00345
CP INPUT
Dn INPUT
Qn OUTPUT
VM
th
VM
VM(1)
th
VI
GND
VI
GND
VOH
VOL
NOTE: the shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3.
Waveforms showing the data set-up and hold times
for the Dn input to the CP input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.


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