データシートサーチシステム |
|
74LV374D データシート(PDF) 7 Page - NXP Semiconductors |
|
74LV374D データシート(HTML) 7 Page - NXP Semiconductors |
7 / 12 page Philips Semiconductors Product specification 74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) 1997 Mar 20 7 AC WAVEFORMS VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. tPLH tPHL SV00343 CP INPUT Qn OUTPUT 1/fmax VM tW 90% VM 10% tTHL tTLH Figure 1. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency outputs disabled SV00344 VI OE INPUT GND VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND VM tPLZ tPHZ tPZL VY outputs enabled outputs enabled VX VM tPZH VM Figure 2. Waveforms showing the 3-state enable and disable times t su t su SV00345 CP INPUT Dn INPUT Qn OUTPUT VM th VM VM(1) th VI GND VI GND VOH VOL NOTE: the shaded areas indicate when the input is permitted to change for predictable output performance. Figure 3. Waveforms showing the data set-up and hold times for the Dn input to the CP input NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. |
同様の部品番号 - 74LV374D |
|
同様の説明 - 74LV374D |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |