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ADM1064ACP データシート(PDF) 4 Page - Analog Devices |
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ADM1064ACP データシート(HTML) 4 Page - Analog Devices |
4 / 32 page ADM1064 Rev. 0 | Page 4 of 32 SPECIFICATIONS VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY ARBITRATION VH, VPn 3.0 V Minimum supply required on one of VPn, VH VP 6.0 V Maximum VDDCAP = 5.1 V, typical VH 14.4 V VDDCAP = 4.75 V VDDCAP 2.7 4.75 5.4 V Regulated LDO output CVDDCAP 10 µF Minimum recommended decoupling capacitance POWER SUPPLY Supply Current, IVH, IVPn 4.2 6 mA VDDCAP = 4.75 V, PDO1–10 off, DACs off, ADC off Additional Currents All PDO FET Drivers On 1 mA VDDCAP = 4.75 V, PDO1-6 loaded with 1 µA each, PDO7–10 off Current Available from VDDCAP 2 mA Maximum additional load that can be drawn from all PDO pull-ups to VDDCAP DACs Supply Current 2.2 mA 6 DACs on with 100 µA maximum load on each ADC Supply Current 1 mA Running round-robin loop EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V SUPPLY FAULT DETECTORS VH Pin Input Attenuator Error ±0.05 % Midrange and high range Detection Ranges High Range 6 14.4 V Midrange 2.5 6 V VPn Pins Input Attenuator Error ±0.05 % Low range and midrange Detection Ranges Midrange 2.5 6 V Low Range 1.25 3 V Ultralow Range 0.573 1.375 V No input attenuation error VX Pins Input Impedance 1 MΩ Detection Ranges Ultralow Range 0.573 1.375 V No input attenuation error Absolute Accuracy ±1 % VREF error + DAC nonlinearity + comparator offset error + input attenuation error Threshold Resolution 8 Bits Digital Glitch Filter 0 µs Minimum programmable filter length 100 µs Maximum programmable filter length ANALOG-TO-DIGITAL CONVERTER Signal Range 0 VREFIN V The ADC can convert signals presented to the VH, VPn, and VX_GPIn pins. VPn and VH input signals are attenuated depending on selected range. A signal at the pin corresponding to the selected range is from 0.573 V to 1.375 V at the ADC input. |
同様の部品番号 - ADM1064ACP |
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同様の説明 - ADM1064ACP |
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