Philips Semiconductors

Product specification

74LV574

Octal D-type flip-flop; positive edge-trigger (3-State)

1998 Jun 10

7

AC WAVEFORMS

output load.

SV00718

GND

CP INPUT

Figure 1. Clock (CP) to output (Qn) propagation delays, the

clock pulse (CP) and the maximum clock pulse frequency

outputs

disabled

SV00344

OE INPUT

GND

OUTPUT

LOW-to-OFF

OFF-to-LOW

OUTPUT

HIGH-to-OFF

OFF-to-HIGH

GND

outputs

enabled

outputs

enabled

Figure 2. 3-state enable and disable times

t

su

t

su

SV00345

CP INPUT

GND

GND

NOTE: the shaded areas indicate when the input is permitted to change

for predictable output performance.

Figure 3.

Data set-up and hold times for the Dn input to the CP

input

NOTE:

The shaded areas indicate when the input is permitted to change for

predictable output performance.

TEST CIRCUIT

SWITCH POSITION

PULSE

GENERATOR

RT

VI

D.U.T.

VO

CL

RL = 1k

VCC

Test Circuit for Outputs

DEFINITIONS

< 2.7V

TEST

2.7V

2.7–3.6V

w 4.5V

50 pF

SV00896

Open

GND

RL = 1k

Open

GND

Figure 4.

Load circuitry for switching times