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74LVC162373ADL データシート(PDF) 10 Page - NXP Semiconductors

部品番号 74LVC162373ADL
部品情報  16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state
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メーカー  PHILIPS [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC162373ADL データシート(HTML) 10 Page - NXP Semiconductors

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2004 Feb 05
10
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30
Ω series termination
resistors; 5 V tolerant inputs/outputs; 3-state
74LVC162373A;
74LVCH162373A
Notes
1. All typical values are measured at Tamb =25 °C.
2. Measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay nDn to nQn
see Fig 6 and 10
1.2
−−−
ns
2.7
1.5
8.5
ns
3.0 to 3.6
1.0
7.5
ns
propagation delay nLE to nQn
see Fig 7 and 10
1.2
−−−
ns
2.7
1.5
9.0
ns
3.0 to 3.6
1.5
8.0
ns
tPZH/tPZL
3-state output enable time nOE to nQn see Fig 8 and 10
1.2
−−−
ns
2.7
1.5
9.5
ns
3.0 to 3.6
1.0
8.0
ns
tPHZ/tPLZ
3-state output disable time nOE to nQn see Fig 8 and 10
1.2
−−−
ns
2.7
1.5
6.0
ns
3.0 to 3.6
1.5
6.0
ns
tW
nLE pulse width HIGH
see Fig 7
1.2
−−−
ns
2.7
3.0
−−
ns
3.0 to 3.6
3.0
−−
ns
tsu
set-up time nDn to nLE
see Fig 9
1.2
−−−
ns
2.7
2.0
−−
ns
3.0 to 3.6
2.0
−−
ns
th
hold time nDn to nLE
see Fig 9
1.2
−−−
ns
2.7
0.9
−−
ns
3.0 to 3.6
0.9
−−
ns
tsk(0)
skew
note 3
3.0 to 3.6
−−
1.5
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)


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