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MC145422DW データシート(PDF) 10 Page - Motorola, Inc |
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MC145422DW データシート(HTML) 10 Page - Motorola, Inc |
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10 / 20 page  MC145422 •MC145426 MOTOROLA 10 Rx Receive Data Voice data is clocked into the UDLT from this pin on the falling edges of TDC/RDC under the control of RE1. RE1 Receive Data Enable 1 Input A rising edge on this pin will enable data on the Rx pin to be loaded into the receive data register on the next eight fall- ing edges of the data dock, TDC/RDC. RE1 and TDC/RDC should be approximately leading–edge aligned. LO1, LO2 Line Driver Outputs These outputs drive the twisted pair line with 256 kHz modified DPSK bursts each frame and are push–pull. These pins are driven to Vref when not modulating the line. MC145426 SLAVE UDLT PIN DESCRIPTIONS VDD Positive Supply Normally 5 V. VSS Negative Supply This pin is the most negative supply pin, normally 0 V. Vref Reference Output This pin is the output of the internal reference supply and should be bypassed to VDD and VSS by 0.1 µF capacitors. No external dc load should be placed on this pin. LI Line Input This input to the demodulator circuit has an internal 100 k Ω resistor tied to the internal reference node (Vref) so that an external capacitor and/or line transformer may be used to couple the signal to this part with no dc offset. LB Loopback Control When this pin is held low and PD is high (the UDLT is re- ceiving transmissions from the master), the UDLT will use the 8 bits of demodulated PCM data in place of the 8 bits of Rx data in the return burst to the Master, thereby looping the part back on itself for system testing. SI1 and SI2 operate normally in this mode. CLK will be held low during loopback operation. VD Valid Data Output A high on this pin indicates that a valid line transmission has been demodulated. A valid transmission is determined by proper sync and the absence of detected bit errors.VD changes state on the leading edge of TE1. If no transmissions from the master have been received in the last 250 µs (derived from the internal oscillator), VD will go low without TE1 rising since TE1 is not generated in the absence of re- ceived transmissions from the master (see TE pin descrip- tion for the one exception to this). SI1, SI2 Signaling Bit Inputs Data on these pins is loaded on the rising edge of TE1 for transmission to the master. If no transmissions from the master are being received and PD is high, data on these pins will be loaded into the part on an internal signal. Therefore, data on these pins should be steady until synchronous communication with the master has been established, as in- dicated by the high on VD. SO1, SO2 Signaling Bit Outputs These outputs are received signaling bits from the master UDLT and change state on the rising edge of TE1. These outputs have standard B–series CMOS output drive capa- bility. PD Power–Down Input/Output This is a bidirectional pin with weak output drivers such that it can be overdriven externally. When held low, the UDLT is powered down and the only active circuitry is that which is necessary for demodulation, TE1/RE1/CLK generation upon demodulation, the outputting of data received from the mas- ter, and updating of VD status. When held high, the UDLT is powered up and transmits in response to transmissions from the master. If no received bursts from the master have oc- curred when powered up for 250 µs (derived from the internal oscillator frequency), the UDLT will generate a free running 125 µs internal clock from the internal oscillator and will burst a transmission to the master every other internal 125 µs clock using data on the SI1 and SI2 pins and the last data word loaded into the receive register. The weak output driv- ers will try to force PD high when a transmission from the master is demodulated and will try to force it low if 250 µs have passed without a transmission from the master. This al- lows the slave UDLT to self power–up and down in demand powered loop systems. TE Tone Enable A high on this pin generates a 500 Hz square wave PCM tone and inserts it in place of the demodulated voice PCM word from the master for outputting to the Tx pin to the telset mono–circuit. A high on TE will generate TE1 and CLK from the internal oscillator when the slave is not receiving bursts from the master so that the PCM square wave can be loaded into the codec–filter. This feature allows the user to provide audio feedback for the telset keyboard depressions except during loopback. During loopback of the slave UDLT, CLK is defeated so a tone cannot be generated in this mode. TE1 Transmit Data Enable 1 Output This is a standard B–series CMOS output which goes high after the completion of demodulation of an incoming transmission from the master. It remains high for 8 CLK periods and then low until the next burst from the master is demodulated. While high, the voice data just demodulated is output on the first eight rising edges of CLK at the Tx pin. The signaling data just demodulated is output on SO1 and SO2 on TE1’s rising edge, as is VD. |
同様の部品番号 - MC145422DW |
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同様の説明 - MC145422DW |
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