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74LVT573DB データシート(PDF) 2 Page - NXP Semiconductors |
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74LVT573DB データシート(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74LVT573 3.3V Octal D-type transparent latch (3-State) 2 1998 Feb 19 853–1750 18988 FEATURES • Inputs and outputs on opposite side of package allow easy interface to microprocessors • 3-State output buffers • Common output enable • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs • Live insertion/extraction permitted • No bus current loading when output is tied to 5V bus • Latch-up protection exceeds 500mA per JEDEC Std 17 • Power-up 3-State • Power-up reset • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay Dn to Qn CL = 50pF; VCC = 3.3V 2.5 2.7 ns CIN Input capacitance VI = 0V or 3.0V 4 pF COUT Output capacitance Outputs disabled; VO = 0V or 3.0V 8 pF ICCZ Total supply current Outputs disabled; VCC = 3.6V .13 mA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 20-Pin Plastic SOL –40 °C to +85°C 74LVT573 D 74LVT573 D SOT163-1 20-Pin Plastic SSOP Type II –40 °C to +85°C 74LVT573 DB 74LVT573 DB SOT339-1 20-Pin Plastic TSSOP Type I –40 °C to +85°C 74LVT573 PW 74LVT573PW DH SOT360-1 PIN CONFIGURATION 10 9 8 7 6 5 4 3 2 120 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E OE D0 D1 D2 D3 D4 D5 D6 D7 GND SV00031 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE Output enable input (active-Low) 2, 3, 4, 5, 6, 7, 8, 9 D0-D7 Data inputs 19, 18, 17, 16, 15, 14, 13, 12 Q0-Q7 Data outputs 11 E Enable input (active-High) 10 GND Ground (0V) 20 VCC Positive supply voltage |
同様の部品番号 - 74LVT573DB |
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同様の説明 - 74LVT573DB |
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