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74LVC2G74DP データシート(PDF) 4 Page - NXP Semiconductors |
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74LVC2G74DP データシート(HTML) 4 Page - NXP Semiconductors |
4 / 20 page 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 4 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 7. Pinning information 7.1 Pinning 7.2 Pin description 8. Functional description 8.1 Function table [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. Fig 4. Pin configuration TSSOP8 and VSSOP8 Fig 5. Pin configuration XSON8 74 CP VCC DSD QRD GND Q 001aab659 1 2 3 4 6 5 8 7 74 RD SD VCC Q Q D CP GND 001aab658 36 27 18 45 Transparent top view Table 4: Pin description Symbol Pin Description CP 1 clock input (LOW-to-HIGH, edge-triggered) D 2 data input Q 3 complement flip-flop output GND 4 ground (0 V) Q 5 true flip-flop output RD 6 asynchronous reset-direct input (active LOW) SD 7 asynchronous set-direct input (active LOW) VCC 8 supply voltage Table 5: Function table for asynchronous operation [1] Input Output SD RD CP D Q Q LH X X H L HL X X L H LLX X H H |
同様の部品番号 - 74LVC2G74DP |
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同様の説明 - 74LVC2G74DP |
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