データシートサーチシステム |
|
AD9411 データシート(PDF) 10 Page - Analog Devices |
|
AD9411 データシート(HTML) 10 Page - Analog Devices |
10 / 28 page AD9411 Rev. A | Page 10 of 28 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the clock command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a low level (–40 dBFS) signal when the adjacent interfering channel is driven by a full- scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the input’s phase 180° and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation 02 . 6 dB 76 . 1 − = MEASURED SNR ENOB Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the clock pulse should be left in the Logic 1 state to achieve rated performance; pulse width low is the minimum time the clock pulse should be left in the low state. Refer to the timing implications of changing tENCH in the Application Notes, Clock Input section. At a given clock rate, these specifications define an acceptable CLOCK duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation: ⎟ ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎜ ⎝ ⎛ = 001 . 0 log 10 2 INPUT RMS FULLSCALE FULLSCALE Z V Power Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The CLOCK rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The CLOCK rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK– and the time when all output data bits are within valid logic levels. |
同様の部品番号 - AD9411 |
|
同様の説明 - AD9411 |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |