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ADF4156BCPZ データシート(PDF) 6 Page - Analog Devices |
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ADF4156BCPZ データシート(HTML) 6 Page - Analog Devices |
6 / 24 page ADF4156 Rev. 0 | Page 6 of 24 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CP CPGND AGND AVDD RFINA RFINB RSET DVDD MUXOUT LE CE REFIN DGND CLOCK DATA VP ADF4156 TOP VIEW (Not to Scale) Figure 3. TSSOP Pin Configuration PIN 1 INDICATOR 1 CPGND 2 AGND 3 AGND 4 RFINB 5 RFINA 13 DATA 14 LE 15 MUXOUT 12 CLOCK 11 CE TOP VIEW (Not to Scale) ADF4156 Figure 4. LFCSP Pin Configuration Table 5. Pin Function Descriptions TSSOP LFCSP Mnemonic Description 1 19 RSET Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between ICP and RSET is SET CPmax R I 5 . 25 = where: RSET = 5.1 kΩ. ICP max = 5 mA. 2 20 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn, drives the external VCO. 3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 5 4 RFINB Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass capacitor, typically 100 pF. 6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO. 7 6, 7 AVDD Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD. 8 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. 9 9, 10 DGND Digital Ground. 10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three- state mode. 11 12 CLOCK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 13 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs serving as the control bits. This input is a high impedance CMOS input. 13 14 LE Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the five latches. The control bits are used to select the latch. 14 15 MUXOUT Multiplexer Output. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. 15 16, 17 DVDD Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD. 16 18 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V. |
同様の部品番号 - ADF4156BCPZ |
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同様の説明 - ADF4156BCPZ |
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