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CS1202 データシート(PDF) 1 Page - Applied Micro Circuits Corporation |
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CS1202 データシート(HTML) 1 Page - Applied Micro Circuits Corporation |
1 / 2 page Features S1202 Block Diagram General Description NILE STS-12 ATM/DS3 SONET MAPPER Part Number S1202 Revision 3.8 - May 2000 AMCC SUMMARY DATASHEET Production Information - The information contained in this document is about a product in its fully tested and character- ized phase. All features described herein are supported. Con- tact AMCC for updates to this document and the latest product status. • Processes valid combinations of SONET/SDH STS-12c/AU-4-4c, STS-3c/AU-4, or STS-1 tributaries within an STS-12/STM-4. • Terminates and generates SONET/SDH section, line, and path layers. • Provides DS3 mapping and demapping for 12 STS-1s and supports clear channel DS3. • Supports ATM payload mapping into STS-12c/AU-4-4c & STS-3c/AU-4, as well as direct ATM or ATM PLCP for DS3 tributaries. • Supports M23 and C-Bit parity clear channel DS3 map- ping, as well as clear channel DS3 transparent passthrough mode. • Provides a 77.76 MHz 8-bit bus interface on the SONET/SDH side in both the TX and RX directions. • Provides a 50 MHz 16-bit Utopia Lvl 2 interface on the sys- tem side in both the TX and RX directions. • Programmable Utopia addresses to support multi-PHY operation. • Generic 8-bit microprocessor interface for configuration and status monitoring. • Supports IEEE 1149.1 JTAG testing. • Packaged in a 388 pin BGA. • Implemented in 3.3V with 5V tolerant I/O. • Loopback capability for SONET/SDH, DS3 and ATM. The S1202 is a highly integrated chip that implements SONET/SDH processing and ATM mapping functions for STS-12/STM-4 data streams. In addition, it supports DS3 tributaries, in an STS-1 SPE, with provisionable support for M23 or C-bit parity OH, as well as clear channel pass-through, direct mapping of ATM cells, or ATM PLCP mapping. The S1202 is SONET and SDH standards compli- ant with Bellcore GR-253 and ANSI T1.105, and ITU G.707, respectively. The S1202 is also DS3 standards compliant with Bellcore GR-499 and ANSI T1.107-1995 and ATM stan- dards compliant with Utopia Specification Level 2. The S1202 supports full-duplex processing of SONET/SDH data streams with section, line, & path overhead processing. The device supports framing, scrambling/descrambling, alarm signal insertion/detection, and bit interleaved parity (B1/B2/B3) processing. Serial interfaces for E1, E2, F1 and Line and Section DCC are also provided. A general purpose 8-bit microprocessor interface is provided for device initialization, control, and monitoring. The interface supports both Intel and Motorola type microprocessors, and is capable of operating in either an interrupt driven or polled-mode configuration. Applications • ATM switches • Packet over SONET Routers and Switches • SONET/SDH Add Drop Multiplexers, Terminal Multiplexers and Digital Cross Connects • Test equipment TX_ATM_DAT[15:0] POINTER INTERPRET POH MONITOR TOH DROP TOH MONITOR RX FRAMER TX FRAMER TOH INSERT SPE/VC GENERATE MICROPROCESSOR I/F JTAG PORT GPIO REG TX_DATA[7:0] TX_CLK78 TX_FRAME_IN RX_DATA[7:0] RX_CLK78 RX_FRAME_OUT RX_EXTLOS 1 12 DS3 1 12 DS3 FR PRBS Det FR PRBS Gen DL Insert DL Drop FEBE TX_DS3[1:4][1:3]DATA RX_DS3[1:4][1:3]FIFO[1:0] 1 12 DS3 Dmap 1 12 DS3 Map 1 12 PLCP 1 12 1 12 ATM 1 12 ATM Proc Proc Proc PLCP Proc Clear Channel DS3 Clear Channel DS3 TX_PRTY TX_SOC TX_CLK TX_ENB TX_ADR[4:0] TX_CLAV[3:0] RX_ATM_DAT[15:0] RX_PRTY RX_SOC RX_CLK RX_ENB RX_ADR[4:0] RX_CLAV[3:0] RX_DS3[1:4][1:3]DATA RX_DS3_x_y_GAP_CLK RX_FRAME_IN TX_DS3[1:4][1:3]CLK RX_DS3_x_y_CLK TX_DS3[1:4][1:3]FIFO TX_DS3[1:4][1:3]X1_IN RX_DS3[1:4][1:3]X1_OUT 1 12 TX FIFO 1 12 RX FIFO RX Utopia I/F Utopia TX I/F |
同様の部品番号 - CS1202 |
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同様の説明 - CS1202 |
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