Preliminary Technical Data

AD7747

Rev. PrC| Page 11 of 20

internal register address. Thus, subsequent transmitted data

bytes are loaded into sequentially incremented addresses.

If a repeated start condition is encountered after the address

pointer byte, all peripherals connected to the bus respond

exactly as outlined above for a start condition, that is, a repeated

start condition is treated the same as a start condition. When a

master device issues a stop condition, it relinquishes control of

the bus, allowing another master device to take control of the

bus. Hence, a master wanting to retain control of the bus issues

successive start conditions known as repeated start conditions.

AD7747 RESET

an explicit reset command is provided. This uses a particular

address pointer word as a command word to reset the part and

upload all default settings. The AD7747 does not respond to the

values upload for approximately 150 µs (max 200 µs).

The reset command address word is 0xBF.

GENERAL CALL

When a master issues a slave address consisting of seven 0s with

the eighth bit (R/W bit) set to 0, this is known as the general call

address. The general call address is for addressing every device

address and read in the following data byte.

If the second byte is 0x06, the AD7747 is reset, completely

uploading all default values. The AD7747 does not respond to

values upload for approximately 150 µs (max 200 µs).

The AD7747 does not acknowledge any other general call

commands.

1–7

8

9

1–7

8

9

1–7

8

9

P

S

START ADDR R/W ACK SUBADDRESS ACK

DATA

ACK

STOP

SDATA

SCLOCK

Figure 10. Bus Data Transfer

DATA

A(S)

S

SLAVE ADDR A(S)

SUB ADDR

A(S)

LSB = 0

LSB = 1

DATA

P

S

SLAVE ADDR A(S)

SUB ADDR

A(S) S

SLAVE ADDR

A(S)

DATA

A(M)

DATA

P

WRITE

SEQUENCE

READ

SEQUENCE

A(S) = NO-ACKNOWLEDGE BY SLAVE

A(M) = NO-ACKNOWLEDGE BY MASTER

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

S = START BIT

P = STOP BIT

A(S)

A(M)

Figure 11. Write and Read Sequences