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LM1212N データシート(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 LM1212N
部品情報  230 MHz Video Amplifier System with OSD Blanking
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM1212N データシート(HTML) 9 Page - National Semiconductor (TI)

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Circuit Description (Continued)
DRIVE CONTROL SECTION
A simplified schematic of the LM1212’s drive control section
is shown in
Figure 6
A 0V to 4V DC voltage is applied at
the drive control input (pin 9) Transistors Q49 Q50 and
Q54 buffer and level shift the contrast voltage to the base of
Q56 The voltage at the emitter of Q56 equals the drive
voltage Vdrive and the current through Q56’s collector is
given by IC56 e Vdrive R43
Transistor Q56’s collector current is used to unbalance the
current through the differential pair comprised of Q58 and
Q60 Q60’s base is internally biased at 71V and connected
to the base of Q12 (see
Figure 3 ) Q58’s base is internally
connected to the base of Q11 (see
Figure 3 ) With Vcont e
2V the differential pair (Q58 Q60) is balanced and the volt-
age at the bases of Q11 and Q12 is 71V Under this condi-
tion Q10’s collector current is equally split between Q11
and Q12 (see
Figure 3 ) If the drive voltage at pin 9 is great-
er than 2V then Q56’s collector current increases thus pull-
ing Q58’s collector node lower and consequently moving
Q58’s base below 71V With base of Q11 below 71V cur-
rent through Q12 (see
Figure 3 ) increases and the amplifi-
er’s gain increases With Vdrive e 4V the amplifier’s gain is
maximum under maximum contrast condition (ie Vcont e
4V)
If the drive voltage at pin 8 is less than 2V then Q56’s col-
lector current decreases and Q58’s base is pulled above
71V With base of Q11 greater than 71V less current flows
through Q12 (see
Figure 3 ) consequently the amplifier’s
gain decreases With Vdrive e 0V the amplifier’s gain is
6 dB less than the maximum gain
CLAMP GATE AND CLAMP COMPARATOR SECTION
Figures 7 and 8 show simplified schematics of the clamp
gate and clamp comparator circuits The clamp gate circuit
(Figure 7) consists of a PNP input buffer transistor (Q82) a
PNP emitter coupled pair (Q85 and Q86) referenced on one
side to 21V and an output switch transistor Q89 When the
clamp gate input at pin 14 is high (l 15V) the Q89 switch is
on and shunts the 200 mA current from current source Q90
to ground When pin 14 is low (k 13V) the Q89 switch is off
and the 200 mA current is mirrored by the current mirror
comprised of Q91 and Q75 (see
Figure 8 ) Consequently
the clamp comparator comprised of the differential pair Q74
and Q77 is enabled The input of the clamp comparator is
similar to the clamp gate except that an NPN emitter cou-
pled pair is used to control the current that will charge or
discharge the clamp capacitor externally connected from
pin 12 to ground PNP transistors are used at the inputs
because they offer a number of advantages over NPNs
PNPs will operate with base voltages at or near ground and
will usually have a greater emitter base breakdown voltage
(BVebo) Because the differential input voltage to the clamp
comparator during the video scan period could be greater
than the BVebo of NPN transistors a resistor (R63) with a
value one half that of R60 or R68 is connected between the
bases of Q71 and Q79 The clamp comparator’s common
mode range is from ground to approximately 9V and the
maximum differential input voltage is VCC
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