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AD7764 データシート(PDF) 8 Page - Analog Devices |
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AD7764 データシート(HTML) 8 Page - Analog Devices |
8 / 21 page AD7764 Preliminary Technical Data Rev. PrC | Page 8 of 21 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VOUTA+ VINA+ VOUTA- AVDD2 VIN+ VIN- VINA- VREF+ REFGND AVDD4 RBIAS AGND1 AVDD1 AGND3 OVERRANGE SCO FSI SDO FSO AVDD2 AGND2 MCLK SYNC SDI RESET/PWRDWN DVDD DEC_RATE AVDD3 AD7764 TOP VIEW (Not to Scale) Figure 5. 28-Lead TSSOP Pin Configuration Table 4. Pin Function Descriptions Pin Number Pin Mnemonic Description 24 AVDD1 +2.5V power supply to the modulator. This pin should be decoupled to pin TBD with a TBDnF capacitor. 7, 21 AVDD2 +5V power supply. Pin 7 should be decoupled to AGND3(pin 8) with a TBD nF capacitor. Pin 21 should be decoupled to AGND1 (pin 23) with a TBD nF capacitor. 28 AVDD3 +3.3V to +5V power supply for on-board differential ampifier. This pin should be decoupled to AGND1 (pin TBD) with a TBDnF capacitor. 25 AVDD4 +3.3V to +5V power supply for on-board reference buffer. This pin should be decoupled to REFGND (pin TBD) with a TBDnF capacitor. 17 DVDD +2.5V power supply for digital circuitry and FIR filter. This pin should be decoupled to the ground plane with a TBDnF capacitor. 22 RBIAS Bias Current setting pin. A resistor must be inserted between this pin and AGND. For more details on this, see the Bias Resistor Section. 23 AGND1 Power Supply ground for analog circuitry. 20 AGND2 Power Supply ground for analog circuitry. 8 AGND3 Power Supply ground for analog circuitry. 26 REFGND Reference Ground. Ground connection for the reference voltage. 27 VREF+ Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4). See Reference Section for more details. 1 VINA- Negative Input to Differential Amplifier. 2 VOUTA+ Positive Output from Differential Amplifier. 3 VINA+ Positive Input to Differential Amplifier. 4 VOUTA- Negative Output from Differential Amplifier. 5 VIN- Negative Input to the Modulator. 6 VIN+ Positive Input to the Modulator. 9 OVERRANGE When this pin outputs a logic high it indicates that the analog input is out of range . This occurs when the magnitude of the differential input is greater than VREF 10 SCO Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal to ICLK. See the AD7764 Interface section for further details. 11 FSO Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. |
同様の部品番号 - AD7764 |
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同様の説明 - AD7764 |
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