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74AUP2G38GM データシート(PDF) 10 Page - NXP Semiconductors |
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74AUP2G38GM データシート(HTML) 10 Page - NXP Semiconductors |
10 / 16 page 74AUP2G38_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 16 October 2006 10 of 16 NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate (open-drain) [1] For measuring enable and disable times RL =5kΩ, for measuring propagation delays, setup and hold times and pulse width RL =1MΩ. Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times 001aac521 PULSE GENERATOR DUT RT VI VO VEXT VCC RL 5 k Ω CL Table 10. Test data Supply voltage Load VEXT VCC CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k Ω or 1 MΩ open GND 2 × VCC |
同様の部品番号 - 74AUP2G38GM |
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同様の説明 - 74AUP2G38GM |
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