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ADN2804 データシート(PDF) 4 Page - Analog Devices

部品番号. ADN2804
部品情報  622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier
ダウンロード  24 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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ADN2804 Datasheet(HTML) 4 Page - Analog Devices

 
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ADN2804
Rev. 0 | Page 4 of 24
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth
OC-12
75
130
kHz
Jitter Peaking
OC-12
0
0.03
dB
Jitter Generation
OC-12, 12 kHz to 5 MHz
0.001
0.003
UI rms
0.011
0.026
UI p-p
Jitter Tolerance
OC-12, 223 − 1 PRBS
30 Hz1
100
UI p-p
300 Hz1
44
UI p-p
25 kHz
2.5
UI p-p
250 kHz1
1.0
UI p-p
1 Jitter tolerance of the ADN2804 at these jitter frequencies is better than what the test equipment is able to measure.


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