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AD7671 データシート(PDF) 9 Page - Analog Devices

部品番号 AD7671
部品情報  18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC
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AD7674
Pin No.
Mnemonic
Type1
Description
13
D6 or
EXT/INT
DI/O
In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an
external clock signal connected to the SCLK input.
14
D7 or
INVSYNC
DI/O
In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the
SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15
D8 or
INVSCLK
DI/O
In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is
active in both master and slave mode.
16
D9 or
RDC/SDIN
DI/O
In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data input
or a read mode selection input depending on the state of EXT/INT. When EXT/ INT is HIGH, RDC/SDIN
could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single
SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the
initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When
RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data
can be output on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground.
18
OVDD
P
Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should
not exceed DVDD by more than 0.3 V.
19
DVDD
P
Digital Power. Nominally at 5 V.
20
DGND
P
Digital Power Ground.
21
D10 or
SDOUT
DO
In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus.
When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7674 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial
mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is valid
on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is valid on
the next rising edge.
In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus.
22
D11 or
SCLK
DI/O
When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.
23
D12 or
SYNC
DO
In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus.
When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid.
When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while
SDOUT output is valid.
24
D13 or
RDERROR
DO
In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus.
In MODE = 3 (serial mode) and when EXT/ INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28
D[14:17]
DO
Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
interface mode.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used
as a data ready clock signal.
30
DGND
P
Must Be Tied to Digital Ground.
31
RD
DI
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7674. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
Rev. 0 | Page 9 of 28


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