ADM1171

Rev. 0 | Page 5 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

2

SS

3

ON

4

8

SENSE

7

CSOUT

6

GATE

5

ADM1171-1AUJ

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration, 1AUJ Model

GND

2

SS

3

ON-CLR

4

8

SENSE

7

CSOUT

6

GATE

5

ADM1171-2AUJ

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration, 2AUJ Model

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

TIMER

Timer Input Pin. The initial and circuit breaker timing cycles are set by this external capacitor. The initial timing

delay is 272.9 ms/μF, and 21.7 ms/μF for a circuit breaker delay. When the TIMER pin is pulled beyond the upper

threshold, the GATE turns off.

2

GND

Chip Ground Pin.

3

SS

Soft Start Pin. An external capacitor between the SS pin and GND sets the ramp rate of the current limit

reference.

4

ON (ON-CLR)

Input Pin. The ON (ON-CLR) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with 80 mV

hysteresis and a glitch filter. The ADM1171 is reset when the ON (ON-CLR) pin is low. When the ON (ON-CLR) pin is

high, the ADM1171 is enabled. A rising edge on this pin has the added function of clearing a fault and restarting

the device on the latched off model, the ADM1171-2.

5

GATE

Gate Output Pin. An internal charge pump provides a 12 μA pull-up current to drive the gate of an N-channel

MOSFET. In an overcurrent condition, the ADM1171 controls the external FET to maintain a constant load

current.

6

CSOUT

gained up by a factor of 20.

7

SENSE

overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV. When this limit is

reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be disabled by connecting the

8

Positive Supply Input Pin. The ADM1171 operates between 2.7 V to 16.5 V. An undervoltage lockout (UVLO)

circuit with a glitch filter resets the ADM1171 when the supply voltage drops below the specified UVLO limit.