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MC68340 データシート(PDF) 38 Page - Freescale Semiconductor, Inc |
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MC68340 データシート(HTML) 38 Page - Freescale Semiconductor, Inc |
38 / 441 page 2- 4 MC68340 USER’S MANUAL MOTOROLA NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 2.2 ADDRESS BUS The address bus signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. The address bus consists of the following two groups. Refer to Section 3 Bus Operation for information on the address bus and its relationship to bus operation. 2.2.1 Address Bus (A23–A0) These three-state outputs (along with A31–A24) provide the address for the current bus cycle, except in the CPU address space. 2.2.2 Address Bus (A31–A24) These pins can be programmed as the most significant eight address bits, port A parallel I/O, or interrupt acknowledge signals. These pins can be used for more than one of their multiplexed functions as long as the external demultiplexing circuit properly resolves interaction between the different functions. A31–A24 These pins can function as the most significant eight address bits. Port A7–A0 These eight pins can serve as a dedicated parallel I/O port. See Section 4 System Integration Module for more information on programming these pins. IACK7– IACK1 The MC68340 asserts one of these pins to indicate the level of an external interrupt during an interrupt acknowledge cycle. Peripherals can use the IACK ≈ signals instead of monitoring the address bus and function codes to determine that an interrupt acknowledge cycle is in progress and to obtain the current interrupt level. 2.3 DATA BUS (D15–D0) This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
同様の部品番号 - MC68340 |
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同様の説明 - MC68340 |
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