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MC68340 データシート(PDF) 55 Page - Freescale Semiconductor, Inc

部品番号. MC68340
部品情報  Integrated Processor with DMA User’s Manual
ダウンロード  441 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
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MC68340 Datasheet(HTML) 55 Page - Freescale Semiconductor, Inc

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MC68340 USER’S MANUAL
MOTOROLA
For example, if the MC68340 is executing an instruction that reads a long-word operand
from a 16-bit port, the MC68340 latches the 16 bits of valid data and runs another bus
cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires
four read cycles. The addressed device uses
DSACK
≈ to indicate the port width. For
instance, a 16-bit device always returns
DSACK
≈ for a 16-bit port (regardless of whether
the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from
a particular port size be fixed. A 16-bit port must reside on data bus bits 15–0, and an 8-bit
port must reside on data bus bits 15–8. This requirement minimizes the number of bus
cycles needed to transfer data to 8- and 16-bit ports and ensures that the MC68340
correctly transfers valid data.
The MC68340 always attempts to transfer the maximum amount of data on all bus cycles;
for a word operation, it always assumes that the port is 16 bits wide when beginning the
bus cycle. The bytes of operands are designated as shown in Figure 3-2. The most
significant byte of a long-word operand is OP0, and OP3 is the least significant byte. The
two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte
of a byte-length operand is OP0. These designations are used in the figures and
descriptions that follow.
Figure 3-2 shows the required organization of data ports on the MC68340 bus for both
8- and 16-bit devices. The four bytes shown in Figure 3-2 are connected through the
internal data bus and data multiplexer to the external data bus. The data multiplexer
establishes the necessary connections for different combinations of address and data
sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their
required positions. The positioning of bytes is determined by the SIZ1/SIZ0 and A0
outputs. The SIZ1/SIZ0 outputs indicate the number of bytes to be transferred during the
current bus cycle (see Table 3-1). The number of bytes transferred during a read or write
bus cycle is equal to or less than the size indicated by the SIZ1/SIZ0 outputs, depending
on port width. For example, during the first bus cycle of a long-word transfer to a word
port, the size outputs indicate that four bytes are to be transferred although only two bytes
are moved on that bus cycle.
The address line A0 also affects the operation of the data multiplexer. During an operand
transfer, A31–A1 indicate the word base address of that portion of the operand to be
accessed, and A0 indicates the byte offset from the base (i.e., either odd or even byte).
Figure 3-2 lists the bytes required on the data bus for read cycles. The entries shown as
OPn are portions of the requested operand that are read or written during that bus cycle
and are defined by SIZ1/SIZ0 and A0 for the bus cycle.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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