データシートサーチシステム |
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MC68340 データシート(PDF) 66 Page - Freescale Semiconductor, Inc |
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MC68340 データシート(HTML) 66 Page - Freescale Semiconductor, Inc |
66 / 441 page MOTOROLA MC68340 USER’S MANUAL 3- 17 State 0—The read cycle starts in state 0 (S0). During S0, the MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the cycle. The MC68340 drives R/ W high for a read cycle. SIZ1/SIZ0 become valid, indicating the number of bytes requested for transfer. State 1—One-half clock later, in state 1 (S1), the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during S1. The selected device uses R/ W, SIZ1 or SIZ0, A0, and DS to place its information on the data bus. One or both of the bytes (D15–D8 and D7–D0) are selected by SIZ1/SIZ0 and A0. State 2—As long as at least one of the DSACK ≈ signals is recognized on the falling edge of S2 (meeting the asynchronous input setup time requirement), data is latched on the falling edge of S4, and the cycle terminates. State 3—If DSACK ≈ is not recognized by the start of state 3 (S3), the MC68340 inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK ≈ on the falling edges of the clock until one is recognized. State 4—At the falling edge of state 4 (S4), the MC68340 latches the incoming data and samples DSACK ≈ to get the port size. State 5—The MC68340 negates AS and DS during state 5 (S5). It holds the address valid during S5 to provide address hold time for memory systems. R/ W, SIZ1 and SIZ0, and FC3–FC0 also remain valid throughout S5. The external device keeps its data and DSACK ≈ signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK ≈ within approximately one clock period after sensing the negation of AS or DS. DSACK ≈ signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
同様の部品番号 - MC68340 |
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同様の説明 - MC68340 |
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