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MC68340 データシート(PDF) 69 Page - Freescale Semiconductor, Inc

部品番号. MC68340
部品情報  Integrated Processor with DMA User’s Manual
ダウンロード  441 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
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MC68340 Datasheet(HTML) 69 Page - Freescale Semiconductor, Inc

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MC68340 USER’S MANUAL
MOTOROLA
State 0—The MC68340 asserts
RMC in S0 to identify a read-modify-write cycle. The
MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The
function codes select the address space for the operation. SIZ1/SIZ0 become valid in S0
to indicate the operand size. The MC68340 drives R/
W high for the read cycle.
State 1—One-half clock later during S1, the MC68340 asserts
AS indicating a valid
address on the address bus. The MC68340 also asserts
DS during S1.
State 2—The selected device uses R/
W, SIZ1/SIZ0, A0, and DS to place information on
the data bus. Either or both of the bytes (D15–D8 and D7–D0) are selected by SIZ1/SIZ0
and A0. Concurrently, the selected device may assert
DSACK
≈.
State 3—As long as at least one of the
DSACK
≈ signals is recognized by the end of S2
(meeting the asynchronous input setup time requirement), data is latched on the next
falling edge of the clock, and the cycle terminates. If
DSACK
≈ is not recognized by the
start of S3, the MC68340 inserts wait states instead of proceeding to S4 and S5. To
ensure that wait states are inserted, both
DSACK1 and DSACK0 must remain negated
throughout the asynchronous input setup and hold times around the end of S2. If wait
states are added, the MC68340 continues to sample the
DSACK
≈ signals on the falling
edges of the clock until one is recognized.
State 4—At the end of S4, the MC68340 latches the incoming data.
State 5—The MC68340 negates
AS and DS during S5. If more than one read cycle is
required to read in the operand(s), S0–S5 are repeated for each read cycle. When
finished reading, the MC68340 holds the address, R/
W, and FC3–FC0 valid in preparation
for the write portion of the cycle. The external device keeps its data and
DSACK
≈ signals
asserted until it detects the negation of
AS or DS (whichever it detects first). The device
must remove the data and negate
DSACK
≈ within approximately one clock period after
sensing the negation of
AS or DS. DSACK
≈ signals that remain asserted beyond this limit
may be prematurely detected for the next portion of the operation.
Idle States—The MC68340 does not assert any new control signals during the idle states,
but it may internally begin the modify portion of the cycle at this time. S0–S5 are omitted if
no write cycle is required. If a write cycle is required, R/
W remains in the read mode until
S0 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not
driven until S2.
State 0—The MC68340 drives R/
W low for a write cycle. Depending on the write operation
to be performed, the address lines may change during S0.
State 1—In S1, the MC68340 asserts
AS, indicating a valid address on the address bus.
State 2—During S2, the MC68340 places the data to be written onto D15–D0.
State 3—The MC68340 asserts
DS during S3, indicating stable data on the data bus. As
long as at least one of the
DSACK
≈ signals is recognized by the end of S2 (meeting the
asynchronous input setup time requirement), the cycle terminates one clock later. If
DSACK
≈ is not recognized by the start of S3, the MC68340 inserts wait states instead of
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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