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AD5624BCPZ-REEL7 データシート(PDF) 7 Page - Analog Devices |
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AD5624BCPZ-REEL7 データシート(HTML) 7 Page - Analog Devices |
7 / 24 page AD5624/AD5664 Rev. 0 | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 VOUTA 10 VREF 2 VOUTB 9 VDD 3 GND 8 DIN 4 VOUTC 7 SCLK 5 VOUTD 6 SYNC AD5624/ AD5664 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 3 GND Ground Reference Point for All Circuitry on the Part. 4 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 8 DIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 9 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 10 VREF Reference Voltage Input. |
同様の部品番号 - AD5624BCPZ-REEL7 |
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同様の説明 - AD5624BCPZ-REEL7 |
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