AD5624R/AD5644R/AD5664R

Rev. A | Page 9 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

10

2

9

3

GND

8

DIN

4

7

SCLK

5

6

SYNC

AD5624R/

AD5644R/

AD5664R

TOP VIEW

(Not to Scale)

EXPOSED PAD TIED TO

GND ON LFCSP PACKAGE

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

3

GND

Ground Reference Point for all Circuitry on the Part.

4

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

5

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

6

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling

interrupt and the write sequence is ignored by the device.

7

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at rates up to 50 MHz.

8

DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.

9

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

10

The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference output. When using the

internal reference, this is the reference output pin. When using an external reference, this is the reference input

pin. The default for this pin is as a reference input.