データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD6624 データシート(PDF) 34 Page - Analog Devices

部品番号 AD6624
部品情報  Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP)
Download  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD6624 データシート(HTML) 34 Page - Analog Devices

Back Button AD6624 Datasheet HTML 30Page - Analog Devices AD6624 Datasheet HTML 31Page - Analog Devices AD6624 Datasheet HTML 32Page - Analog Devices AD6624 Datasheet HTML 33Page - Analog Devices AD6624 Datasheet HTML 34Page - Analog Devices AD6624 Datasheet HTML 35Page - Analog Devices AD6624 Datasheet HTML 36Page - Analog Devices AD6624 Datasheet HTML 37Page - Analog Devices AD6624 Datasheet HTML 38Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 34 / 40 page
background image
REV. B
AD6624
–34–
External Memory Map
When broadcast is enabled (Bit 6 set high), readback is not valid
because of the potential for internal bus contention. Therefore,
if readback is subsequently desired, the broadcast bit should
be set low.
Bits 1–0 of this register are address bits that decode which of the
four channels are being accessed. If the Instruction bits decode
an access to multiple channels, these bits are ignored. If the
Instruction decodes an access to a subset of chips, the A[9:8] bits
will otherwise determine the channel being accessed.
Channel Address Register (CAR)
This register represents the 8-bit internal address of each channel.
If the autoincrement bit of the ACR is 1, this value will be incre-
mented after every access to the DR0 register, which will in
turn access the location pointed to by this address. The Channel
Address register cannot be read back while the broadcast bit
is set high.
SOFT_SYNC Control Register
External Address [5] is the SOFT_SYNC control register and is
write only.
Bits 0–3 of this register are the SOFT_SYNC control bits. These
pins may be written to by the controller to initiate the synchro-
nization of a selected channel. Although there are four inputs,
these do not necessarily go to the channel of the same number.
This is fully configurable at the channel level as to which bit to
look at. All four channels may be configured to synchronize from a
single position, or they may be paired or all independent.
Bit 4 determines if the synchronization is to apply to a chip
start. If this bit is set, a chip start will be initiated.
Bit 5 determines if the synchronization is to apply to a chip hop.
If this bit is set, the NCO frequency will be updated when the
SOFT_SYNC occurs.
Bit 6 configures how the internal databus is configured. If this
bit is set low, the internal ADC databuses are configured nor-
mally. If this bit is set, the internal test signals are selected. The
internal test signals are configured in Bit 7 of this register.
Bit 7 if set clear, a negative full-scale signal is generated and
made available to the internal databus. If this bit is high, inter-
nal pseudo-random sequence generator is enabled and this data
is available to the internal databus. The combined functions of
Bits 6 and 7 facilitate verification of a given filter design and in
conjunction with the MISR registers, allow for detailed in-system
chip testing. In conjunction with the JTAG test board, very high
levels of chip verification can be done during system test, in both
the factory and field.
PIN_SYNC Control Register
External Address [4] is the PIN_SYNC control register and is
write only.
Bits 0–3 of this register are the SYNC_EN control bits. These
pins may be written to by the controller to allow pin synchroni-
zation of a selected channel. Although there are four inputs,
these do not necessarily go to the channel of the same number.
This is fully configurable at the channel level as to which bit to
look at. All four channels may be configured to synchronize
from a single position, or they may be paired or all independent.
Bit 4 determines if the synchronization is to apply to a
chip start. If this bit is set, a chip start will be initiated
PIN_SYNC occurs.
Bit 5 determines if the synchronization is to apply to a chip hop.
If this bit is set, the NCO Frequency will be updated when the
PIN_SYNC occurs.
Bit 6 is used to ignore repetitive synchronization signals. In
some applications, this signal may occur periodically. If this bit
is clear, each PIN_SYNC will restart/hop the channel. If this bit
is set, only the first occurrence will cause the chip to take action.
Bit 7 is used with Bits 6 and 7 of external address 5. When this
bit is cleared, the data supplied to the internal databus simulates
a normal ADC. When this bit is set, the data supplied is in the
form of a time-multiplexed ADC such as the AD6600 (this
allows the equivalent of testing in the 4-channel input mode).
Internally, when set, this bit forces the IEN pin to toggle as if it
were driven by the A/B signal of the AD6600.
SLEEP Control Register
External Address [3] is the sleep register.
Bits 3–0 control the state of each of the channels. Each bit corre-
sponds to one of the possible RSP channels within the device. If
this bit is cleared, the channel operates normally. However,
when this bit is set, the indicated channel enters a low-power
sleep mode.
Table XIII. Memory Map for Input Port Control Registers
Ch Address
Register
Bit Width
Comments
00
Lower Threshold A
10
9–0:
Lower Threshold for Input A
01
Upper Threshold A
10
9–0:
Upper Threshold for Input A
02
Dwell Time A
20
19–0:
Minimum Time below Lower Threshold A
03
Gain Range A Control Register
5
4:
Output Polarity LIA-A and LIA-B
3:
Interleaved Channels
2–0:
Linearization Hold-Off Register
04
Lower Threshold B
10
9–0:
Lower Threshold for Input B
05
Upper Threshold B
10
9–0:
Upper Threshold for Input B
06
Dwell Time B
20
19–0:
Minimum Time below Lower Threshold B
07
Gain Range B Control Register
5
4:
Output Polarity LIB-A and LIB-B
3:
Interleaved Channels
2–0:
Linearization Hold-Off Register


同様の部品番号 - AD6624

メーカー部品番号データシート部品情報
logo
Analog Devices
AD6624A AD-AD6624A Datasheet
636Kb / 40P
   Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
REV. 0
AD6624AABC AD-AD6624AABC Datasheet
636Kb / 40P
   Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
REV. 0
AD6624AS/PCB AD-AD6624AS/PCB Datasheet
636Kb / 40P
   Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
REV. 0
AD6624A AD-AD6624A_15 Datasheet
642Kb / 40P
   Four-Channel, 100 MSPS Digital Receive Signal Processor
REV. 0
AD6624 AD-AD6624_15 Datasheet
566Kb / 40P
   Four-Channel, 80 MSPS Digital Receive Signal Processor
REV. B
More results

同様の説明 - AD6624

メーカー部品番号データシート部品情報
logo
Analog Devices
AD6624A AD-AD6624A Datasheet
636Kb / 40P
   Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
REV. 0
AD6624 AD-AD6624_15 Datasheet
566Kb / 40P
   Four-Channel, 80 MSPS Digital Receive Signal Processor
REV. B
AD6635 AD-AD6635 Datasheet
799Kb / 60P
   4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
REV. 0
AD6634 AD-AD6634 Datasheet
925Kb / 52P
   80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP)
REV. 0
AD6624A AD-AD6624A_15 Datasheet
642Kb / 40P
   Four-Channel, 100 MSPS Digital Receive Signal Processor
REV. 0
AD6634 AD-AD6634_15 Datasheet
931Kb / 52P
   80 MSPS, Dual-Channel WCDMA Receive Signal Processor
REV. 0
AD6635 AD-AD6635_15 Datasheet
805Kb / 60P
   4-Channel, 80 MSPS WCDMA Receive Signal Processor
REV. 0
AD6620ASZ AD-AD6620ASZ Datasheet
374Kb / 44P
   67 MSPS Digital Receive Signal Processor
REV. A
AD6620 AD-AD6620 Datasheet
354Kb / 43P
   65 MSPS Digital Receive Signal Processor
REV. 0
AD6620 AD-AD6620_15 Datasheet
399Kb / 44P
   67 MSPS Digital Receive Signal Processor
REV. A
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com