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AD7366ARUZ-REEL7 データシート(PDF) 6 Page - Analog Devices |
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AD7366ARUZ-REEL7 データシート(HTML) 6 Page - Analog Devices |
6 / 17 page AD7366 Preliminary Technical Data Rev. PrG | Page 6 of 17 TIMING SPECIFICATIONS AVCC = DVCC =4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = −11.5 V to −16.5 V, VDRIVE = 2.7 V to 5.25V, TA = TMIN to TMAX, unless otherwise noted1. Table 3. Parameter Limit at TMIN, TMAX Unit Test Conditions / Comments 2.7V≤VDRIVE<4.75V 4.75V≤VDRIVE≤5.25V tCONVERT 610 610 ns max Conversion time, Internal clock. CONVST falling edge to BUSY falling edge fSCLK 10 10 kHz min Frequency of serial read clock. 35 48 MHz max tQUIET 30 30 ns min Minimum quiet time required between end of serial read and start of next conversion t1 10 10 ns min Minimum CONVST Low pulse. t2 5 5 ns min CONVST falling edge to BUSY rising edge. t3 0 0 ns min BUSY falling edge to MSB valid once CS is low for t4 prior to BUSY going Low t4 10 10 ns max Delay from CS falling edge until DOUTA and DOUTB are three-state disabled t52 20 14 ns max Data access time after SCLK falling edge t6 5 5 ns min SCLK to data valid hold time t7 0.1 tSCLK 0.1 tSCLK ns min SCLK low pulse width t8 0.1 tSCLK 0.1 tSCLK ns min SCLK high pulse width t9 10 10 ns max CS rising edge to DOUTA, DOUTB, high impedance t10 5 5 ns min SCLK falling edge to DOUTA, DOUTB, high impedance 10 10 ns max SCLK falling edge to DOUTA, DOUTB, high impedance tPOWER-UP 70 70 μs Power up time from shutdown mode. Time required between CONVST rising edge and CONVST falling edge. 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See Terminology section and Figure 9. 2 The time required for the output to cross 0.4 V or 2.4 V. |
同様の部品番号 - AD7366ARUZ-REEL7 |
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同様の説明 - AD7366ARUZ-REEL7 |
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