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AD7367BRUZ データシート(PDF) 10 Page - Analog Devices |
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AD7367BRUZ データシート(HTML) 10 Page - Analog Devices |
10 / 16 page AD7367 Preliminary Technical Data Rev. PrD | Page 10 of 16 PSRR (Power Supply Rejection) Variations in power supply affect the full-scale transition but not the converter’s linearity. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see figure x). THEORY OF OPERATION Circuit Information The AD7367 is a fast, dual, 2-Channel, 14-bit, Bipolar Input, Serial A/D converter. The AD7367 can accept bipolar input ranges of ±10V and ±5V. It can also accept a 0 to 10V unipolar input range. The AD7367 requires VDD and VSS dual supplies for the high voltage analog input structure. These supplies must be equal to or greater than 11.5V. See Table 6 for the minimum requirements on these supplies for each Analog Input Range. The AD7367 requires a low voltage 4.75V to 5.25 V VCC supply to power the ADC core. Table 6. Reference and Supply Requirements for each Analog Input Range Selected Analog Input Range (V) Reference Voltage (V) Full Scale Input Range(V) AVCC (V) Minimum VDD/VSS (V) 2.5 ±10 5 ±11.5 ±10 3.0 ±12 5 ±12 2.5 ±5 5 ±11.5 ± 5 3.0 ±6 5 ±11.5 2.5 0 to 10 5 ±11.5 0 to 10 3.0 0 to 12 5 ±12 The AD7367 contains two on-chip differential track-and-hold amplifiers, two successive approximation A/D converters, and a serial interface with two separate data output pins. It is housed in a 24-lead TSSOP package, offering the user considerable space-saving advantages over alternative solutions. The AD7367 requires a CONVST signal to start conversion. On the falling edge of CONVST both track-and-holds will be placed into hold mode and the conversions are initiated. The BUSY signal will go high to indicate the conversions are taking place. The clock source for each successive approximation ADC is provided by an internal oscillator. The BUSY signal will go low to indicate the end of conversion. On the falling edge of BUSY the track- and-hold will return to track mode. Once the conversion is finished, the serial clock input accesses data from the part. The AD7367 has an on-chip 2.5 V reference that can be overdriven when an external reference is preferred. If the internal reference is to be used elsewhere in a system, then the output from DCAPA & DCAPB must first be buffered. On Power up the REFSEL pin must be tied to either a high or low logic state to select either the internal or external reference option. If the internal reference is the preferred option, the user must tie the REFSEL pin logic high. Alternatively, if REFSEL is tied to GND then an external reference can be supplied to both ADC’s through DCAPA & DCAPB pins. The analog inputs are configured as two single ended inputs for each ADC. The various different input voltage ranges can be selected by programming the RANGE bits as shown in Table 7. The AD7367 also features power-down option to allow power saving between conversions. The power-down feature is implemented via the CONVST pin as described in the Modes of Operation section. Converter Operation The AD7367 has two successive approximation analog-to- digital converters, each based around two capacitive DACs. Figure 3 and Figure 4 show simplified schematics of one of these ADCs in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 3 (the acquisition phase), SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the signal on the input. VIN AGND A B SW1 SW2 COMPARATOR CAPACITIVE DAC CONTROL LOGIC Figure 3 ADC Acquisition Phase When the ADC starts a conversion (Figure 4), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. |
同様の部品番号 - AD7367BRUZ |
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同様の説明 - AD7367BRUZ |
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