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MYSON
TECHNOLOGY
MTV212M32
(Rev 1.1)
Revision 1.1
- 10 -
2000/07/04
Reg name
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DA0
20h (r/w)
Pulse width of PWM DAC 0
DA1
21h (r/w)
Pulse width of PWM DAC 1
DA2
22h (r/w)
Pulse width of PWM DAC 2
DA3
23h (r/w)
Pulse width of PWM DAC 3
DA4
24h (r/w)
Pulse width of PWM DAC 4
DA5
25h (r/w)
Pulse width of PWM DAC 5
DA6
26h (r/w)
Pulse width of PWM DAC 6
DA7
27h (r/w)
Pulse width of PWM DAC 7
DA8
28h (r/w)
Pulse width of PWM DAC 8
DA9
29h (r/w)
Pulse width of PWM DAC 9
DA10
2Ah (r/w)
Pulse width of PWM DAC 10
DA11
2Bh (r/w)
Pulse width of PWM DAC 11
DA12
2Ch (r/w)
Pulse width of PWM DAC 12
DA13
2Dh (r/w)
Pulse width of PWM DAC 13
DA0-13 (r/w) :
The output pulse width control for DA0-13.
* All of PWM DAC converters are centered with value 80h after power on.
6. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion, SYNC
inputs presence check, frequency counting, polarity detection and control, as well as the protection of
VBLANK output while VSYNC speed up in high DDC communication clock rate. The present and frequency
function block treat any pulse shorter than one OSC period as noise.
Hself
Hpol
CVpre
Vbpl
VSYNC
Digital Filter
Polarity Check &
Sync Seperator
Vpre
Present
Check
Vfreq
Vpol
Polarity Check &
Freq. Count
XOR
VBLANK
Vself
XOR
HSYNC
Digital Filter
CVSYNC
Present
Check
Hpre
Hfreq
Present Check &
Freq. Count
Hbpl
XOR
HBLANK
XOR
Composite
Pulse Insert
H/V SYNC Processor Block Diagram
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