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P89LPC9401 データシート(PDF) 27 Page - NXP Semiconductors |
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P89LPC9401 データシート(HTML) 27 Page - NXP Semiconductors |
27 / 59 page P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Preliminary data sheet Rev. 01 — 5 September 2005 27 of 59 Philips Semiconductors P89LPC9401 8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 1 ⁄ 16 or 1 ⁄ 32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. 7.19.4 Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 7.19.5 “Baud rate generator and selection”). 7.19.5 Baud rate generator and selection The P89LPC9401 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 8). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses OSCCLK. 7.19.6 Framing error Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is logic 0. 7.19.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode. 7.19.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Fig 8. Baud rate sources for UART (Modes 1, 3) baud rate modes 1 and 3 SBRGS = 1 SBRGS = 0 SMOD1 = 0 SMOD1 = 1 timer 1 overflow (PCLK-based) baud rate generator (CCLK-based) 002aaa897 ÷2 |
同様の部品番号 - P89LPC9401 |
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同様の説明 - P89LPC9401 |
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