AD8364ACPZ-RL21 datasheet(6/48 Pages) AD

部品番号	AD8364ACPZ-RL21

部品情報	LF to 2.7 GHz Dual 60 dB TruPwr Detector

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AD8364

Rev. 0 | Page 6 of 48

Parameter

Conditions

Min

Typ

Max

Unit

SETPOINT INPUT

Pin VSTA and VSTB

Voltage Range

Law conformance error ≤1 dB

0.5

3.75

V

Input Resistance

68

kΩ

Logarithmic Scale Factor

f = 450 MHz, −40°C ≤ TA ≤ +85°C

50

mV/dB

Logarithmic Intercept

f = 450 MHz, −40°C ≤ TA ≤ +85°C, referred to 50 Ω

−55

dBm

CHANNEL DIFFERENCE OUTPUT

Pin OUTP and OUTN

Voltage Range Min

RL ≥ 200 Ω to ground

0.1

V

Voltage Range Max

RL ≥ 200 Ω to ground

VS − 0.15

V

Source/Sink Current

OUTP and OUTN held at VS/2, to 1% change

70

mA

DIFFERENCE LEVEL ADJUST

Pin VLVL

Voltage Range3

OUT[P, N] = FBK[A, B]

0

5

V

OUT[P,N] Voltage Range

OUT[P, N] = FBK[A, B]

0

VS −

0.15

V

Input Resistance

1

kΩ

TEMPERATURE COMPENSATION

Pin ADJA and ADJB

Input Voltage Range

0

2.5

V

Input Resistance

>1

MΩ

VOLTAGE REFERENCE

Pin VREF

Output Voltage

RF in = −55 dBm

2.5

V

Temperature Sensitivity

−40°C ≤ TA ≤ +85°C

0.4

mV/°C

Current Limit Source/Sink

1% change

10/3

mA

TEMPERATURE REFERENCE

Pin TEMP

Output Voltage

TA = 25°C, RL ≥ 10 kΩ

0.62

V

Temperature Coefficient

−40°C ≤ TA ≤ +85°C, RL ≥ 10 kΩ

2

mV/°C

Current Source/Sink

TA = 25°C to 1% change

1.6/2

mA

POWER-DOWN INTERFACE

Pin PWDN

Logic Level to Enable

Logic LO enables

1

V

Logic Level to Disable

Logic HI disables

3

V

Input Current

Logic HI PWDN = 5 V

95

µA

Logic LO PWDN = 0 V

<100

µA

Enable Time

PWDN LO to OUTA/OUTB at 100% final value,

CLPA/B = Open, CHPA/B = 10 nF, RF in = 0 dBm

2

µs

Disable Time

PWDN HI to OUTA/OUTB at 10% final value,

CLPA/B = Open, CHPA/B = 10nF, RF in = 0 dBm

1.6

µs

POWER INTERFACE

Pin VPS[A, B], VPSR

Supply Voltage

4.5

5.5

V

Quiescent Current

RF in = −55 dBm, VS = 5 V

70

mA

−40°C ≤ TA ≤ +85°C

90

mA

Supply Current

PWDN enabled, VS = 5 V

500

µA

−40°C ≤ TA ≤ +85°C

900

µA

1 Best fit line, linear regression.

2 See

for a plot of isolation vs. frequency for a ±1 dB error.

Figure 75

3 VLVL + OUTA/2 should not exceed VPSA − 1.31 V. Likewise, VLVL + OUTB/2 should not exceed VPSB − 1.31 V.

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AD8364ACPZ-RL21 データシート(PDF) 6 Page - Analog Devices

AD8364ACPZ-RL21 データシート(HTML) 6 Page - Analog Devices

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