AD9923ABBCZ datasheet(66/88 Pages) AD

部品番号	AD9923ABBCZ

部品情報	CCD Signal Processor with V-Driver and Precision Timing??Generator

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AD9923A

Rev. 0 | Page 66 of 88

SERIAL INTERFACE TIMING

All of the AD9923A internal registers are accessed through a

3-wire serial interface. Each register consists of a 12-bit address

and a 28-bit data-word. Both the address and data-word are

written by starting with the LSB. To write to each register, a 40-bit

operation is required, as shown in Figure 84. Although many

data-words are fewer than 28 bits wide, all 28 bits must be

written for each register. For example, if the data-word is only

20 bits wide, the upper 8 bits are don’t cares and must be filled

with 0s during the serial write operation. If fewer than 28 data

bits are written, the register is not updated with new data.

Figure 85 shows a more efficient way to write to the registers,

using the AD9923A address auto-increment capability. Using

this method, the lowest desired address is written first, followed

by multiple 28-bit data-words. Each data-word is automatically

written to the address of the next highest register. By eliminating

the need to write each address, faster register loading is achieved.

Continuous write operations can start with any register location.

A4

A5

A2

A3

SDI

A0

A1

A6

A8

A9

A10 A11

D0

D1

D2

D3

D25

D26 D27

SL

A7

tLS

tDS

12-BIT ADDRESS

28-BIT DATA

5

40

6

7

8

9

10

11

12

13

14

15

16

38

39

tLH

tDH

NOTES

1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.

2. ALL 40 BITS MUST BE WRITTEN: 12 BITS FOR ADDRESS AND 28 BITS FOR DATA-WORD.

3. IF THE DATA-WORD IS <28 BITS, 0s MUST BE USED TO COMPLETE THE 28-BIT DATA-WORD LENGTH.

4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE

PARTICULAR REGISTER WRITTEN TO. SEE THE UPDATING OF NEW REGISTER VALUES SECTION FOR MORE INFORMATION.

SCK

12

34

Figure 84. Serial Write Operation

SDI

A0

A1

A2

A10 A11

D0

D1

D26 D27

SCK

SL

A3

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 28-BIT DATA-WORDS.

3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 28-BIT DATA-WORD (ALL 28 BITS MUST BE WRITTEN).

4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER IS LOADED.

D0

D1

D26

D27

D0

DATA FOR STARTING

REGISTER ADDRESS

DATA FOR NEXT

REGISTER ADDRESS

D2

D1

1

40

2

3

4

1112

1314

39

42

41

68

67

70

69

71

Figure 85. Continuous Serial Write Operation

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