AD9927 datasheet(37/100 Pages) AD

部品番号	AD9927

部品情報	14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator

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AD9927

Rev. 0 | Page 37 of 100

Using the LASTREPLEN_EN

The LASTREPLEN_EN register (Address 0x00, Bits [19:16] in

the sequence registers) is used to enable a separate pattern

length to be used in the final repetition of several pulse

repetitions. It is recommended that the LASTREPLEN_EN

register bits be set high (enabled) and the LASTREPLEN_A,

LASTREPLEN_B, LASTREPLEN_C, AND LASTREPLEN_D

registers be set to a value equal to the VLENA, VLENB,

VLENC, and VLEND register values, respectively.

Generating Line Alternation for V-Sequences and HBLK

During low resolution readout, some CCDs require a different

number of vertical clocks on alternate lines. The AD9927 can

support this by using the VREP registers. This allows a different

number of V-pattern group repetitions to be programmed on

odd and even lines. Only the number of repeats can be different

in odd and even lines, while the V-pattern group remains the

same. There are separate controls for the assigned Group A,

Group B, Group C, and Group D patterns. All groups can

support odd and even line alternation. Group A uses the

VREPA_1 and VREPA_2 registers; Group B, Group C, and

Group D use the corresponding VREP_ODD and VREP_EVEN

registers. With the additional VREPA_3 and VREPA_4

registers, Group A can also support 3-line and 4-line

alternation.

As discussed in the Generating HBLK Line Alternation section,

the HBLK signal can be alternated for odd and even lines.

Figure 43 shows an example of V-pattern group repetition

alternation and HBLK Mode 0 alternation used together.

XV1

XV2

XV24

HD

HBLK

TOGE1

TOGE2

TOGO1

TOGO2

TOGE1

TOGE2

NOTES

1. THE NUMBER OF REPEATS FOR V-PATTERN GROUPS A/B/C/D CAN BE ALTERNATED ON ODD AND EVEN LINES.

2. GROUP A ALSO SUPPORTS 3- AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS.

3. THE HBLK TOGGLE POSITIONS CAN BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS.

VREPA_1 = 2

(OR VREPB/C/D_EVEN = 2)

VREPA_2 = 5

(OR VREPB/C/D_ODD = 5)

VREPA_1 = 2

(OR VREPB/C/D_EVEN = 2)

Figure 43. Odd/Even Line Alternation of V-Pattern Group Repetitions and HBLK Toggle Positions

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Analog Devices	AD9927	843Kb / 100P	14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator REV. 0

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