AD9927 datasheet(6/100 Pages) AD

部品番号	AD9927

部品情報	14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator

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AD9927

Rev. 0 | Page 6 of 100

TIMING SPECIFICATIONS

CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK (See Figure 16)

CLI Clock Period

tCONV

25

ns

CLI High/Low Pulse Width

10

12.5

15

ns

Delay from CLI Rising Edge to Internal Pixel Position 0

tCLIDLY

6

ns

VD FALLING EDGE TO HD FALLING EDGE IN SLAVE MODE (See Figure 89)

tVDHD

0

VD period − 5 × tCONV

ns

AFE CLPOB PULSE WIDTH (See Figure 23 and Figure 33)1, 2

2

20

Pixels

AFE SAMPLE LOCATION (See Figure 17 and Figure 20)1

SHP Sample Edge to SHD Sample Edge

tS1

11

12.5

ns

DATA OUTPUTS (See Figure 21 and Figure 22)

Output Delay from DCLK Rising Edge

tOD

1

ns

Inhibited Area for DOUTPHASE Edge Location

tDOUTINH

SHDLOC + 1

SHDLOC + 15

Edge

location

Pipeline Delay from SHP/SHD Sampling to DOUT

16

Cycles

SERIAL INTERFACE (See Figure 97)

Maximum SCK Frequency (Must Not Exceed CLI Frequency)

fSCLK

40

MHz

SL to SCK Setup Time

tLS

10

ns

SCK to SL Hold Time

tLH

10

ns

SDATA Valid to SCK Rising Edge Setup

tDS

10

ns

SCK Falling Edge to SDATA Valid Hold

tDH

10

ns

1 Parameter is programmable.

2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

同様の部品番号 - AD9927

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