TCH305-0001-002
5
SUBJECT TO CHANGE
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The four-channel DMA controller provides high-bandwidth communication between CSL-
based I/O devices, at up to 228M bytes per second, per direction. The easy-to-use DMA
handshake simplifies interface and control logic within the CSL. The DMA controller pro-
vides advanced capabilities such as linked-list and frame-transfer support.
Dedicated Peripherals
The A7S also offers a set of common dedicated peripherals including
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two 16-bit timers with pre-scalers,
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two 16C450/550-like serial controllers (UART), with an optional modem interface
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a 32-bit watchdog timer, and
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an interrupt controller.
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The majority of the system, including the CPU, operates from a single clock signal. The
clock source is typically driven directly via an external pin or connected to the on-chip PLL
clock synthesizer. The clock synthesizer operates from an external 32.768 kHz watch
crystal. Additionally, an internal ring oscillator is provided. Six other global buffers pro-
vide high-fanout signals to CSL functions. The bus clock and the global buffers are op-
tionally stopped upon a breakpoint event and shut off during power-down mode.
Power management controls provide selectable power-down options over internal func-
tions. Furthermore, each PIO provides pin-by-pin power-down settings.
An internal initialization boot ROM controls device initialization after power-on or after the
reset pin is released. The initialization boot ROM locates user's initialization data and
code stored in external Flash or other non-volatile memory. The Triscend FastChip de-
velopment system programs external Flash via the A7S’s JTAG port.
Additionally, the JTAG interface provides real-time, in-system debugging capabilities,
eliminating the need for an external emulator. The JTAG interface has full access and
control over the CPU, peripherals, and CSL functions during debugging.
When debugging application software, the A7S employs the rich set of standard
ARM7TDMI debugging tools. The A7S fully supports the standard ARM internal break-
point and watchpoint capabilities. In addition, the A7S’s breakpoint unit monitors both the
CPU local bus or the CSI bus. Upon a predefined set of conditions, the breakpoint unit
halts or interrupts the execution of the application program. The breakpoint unit also sup-
ports real-time tracing of local CPU bus or the CSI bus transactions.
All together, the Triscend A7S Configurable System-on-Chip (CSoC) platform offers un-
paralleled time-to-market and performance advantages for embedded system designs.
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