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Triscend A7S Configurable System-on-Chip Platform
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TCH305-0001-002
ARM7TDMI Processor Overview
The A7S Configurable System-on-Chip family includes an embedded ARM7TDMI 32-bit
RISC processor. The A7S is binary compatible with other ARM7-based devices. Figure 4
shows the major architectural features within the ARM7TDMI processor and the following
text provides a brief overview. Please refer to the ARM7TDMI data sheet or Resources
for more additional information.
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Registers
The ARM7TDMI CPU has sixteen active 32-bit general-purpose registers at any given in-
stance. There are a total of 31 such registers but some are only available during excep-
tion handling.
Register Bank
(31x32-bit registers)
(6 status register)
Address
Incrementer
Address Register
Write Data Register
Instruction Pipeline
Read Data Register
Thumb Instruction Decoder
32 x 8
Multiplier
32-bit ALU
Barrel
Shifter
Address[31:0]
Write Data[31:0]
Read Data[31:0]
Figure 4. ARM7TDMI CPU Block Diagram.