データシートサーチシステム |
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CDB42L52 データシート(PDF) 7 Page - Cirrus Logic |
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CDB42L52 データシート(HTML) 7 Page - Cirrus Logic |
7 / 26 page DS680DB1 7 CDB42L52 2.1 Board Configuration Tab The “Board Configuration” tab provides high-level control of signal routing on the CDB42L52. This tab also includes basic controls that allow “quick setup” in a number of simple board configurations. Status text de- tailing the CODEC’s specific configuration appears directly below the associated control. This text may change depending on the setting of the associated control. A description of each control group is outlined below: CS42L52 CODEC Basic Configuration - Register controls for CS42L52 basic setup like interface format, clocking functions and analog input signal routing. See Section 2.2 through Section 2.5 for more controls in the CS42L52. CS8416 S/PDIF Receiver Control - Register controls for setting up the CS8416. CS8406 S/PDIF Transmitter Control - Register controls for setting up the CS8406. Clock/Data Routing and Selection - Includes controls used for routing clocks and data between the CS42L52, CS8416, oscillator, I/O stake header, SRC and PFD. Also includes a reset control for the CS42L52. Update - Reads all registers in the FPGA, CS42L52 and CS8421 and shows the current values in the GUI. Reset - Resets FPGA to default routing configuration. Figure 1. Board Configuration Tab |
同様の部品番号 - CDB42L52 |
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同様の説明 - CDB42L52 |
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