Optimized for
5
TM
Table 2: CS5010-40 DES/3DES Cores Interface Signal Definitions
Signal
I/O
Width (Bits)
Description
D
I
32 (64 Ultra High Speed)
Input Plaintext/Ciphertext data
DADDR
I
1 (Ultra Compact)
2 (Compact)
3 (High Speed)
0 (Ultra High Speed)
Input Plaintext/Ciphertext data address, 0: the lowest 32-bit word
DLOAD
I
1
Load input Plaintext/Ciphertext enable
KEY
I
28 (56 Ultra High Speed)
Encryption key data
KADDR
I
2
Encryption key address, 0: the lowest 28-bit word
KLOAD
I
1
Load encryption key
MODE
I
1
Encryption/Decryption mode select, 0: Encryption. 1: Decryption
TRIPLE
I
1
DES/3DES mode select, 0: DES, 1:3DES
EDE
I
1
Triple DES key selection mode, 0:EDE2, 1: EDE3
CLK
I
1
System clock, rising edge active
RST
I
1
Asynchronous reset
DSTAT
O
1
Input port status
This signal will be Asserted when the core is ready for loading the
highest word of the next 64-bit data block, or the highest word of the
multiple input DES blocks available in the Compact or High Speed
cores. The lower words can be loaded at anytime in the period
when DSTAT is LOW depending on the key-size selection
QSTRB
O
1
Output strobe indicating the Plaintext/Ciphertext word Q is valid
QADDR
O
1 (Ultra Compact)
2 (Compact)
3 (High Speed)
0 (Ultra High Speed)
Output Plaintext/Ciphertext data address, 0: the lowest 32-bit word
Q
O
32 (64 Ultra High Speed)
Output Plaintext/Ciphertext data
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