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IDT74ALVCH374 データシート(PDF) 5 Page - Integrated Device Technology

部品番号 IDT74ALVCH374
部品情報  3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
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メーカー  IDT [Integrated Device Technology]
ホームページ  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT74ALVCH374 データシート(HTML) 5 Page - Integrated Device Technology

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5
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH374
3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
Open
VLOAD
GND
VCC
Pulse
Generator
D.U .T.
500
500
CL
RT
VIN
VOUT
(1, 2)
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OUTPU T 1
OUTPU T 2
tPHL1
tSK (x)
tPLH2
tPHL2
VT
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
DATA
INPUT
0V
0V
0V
0V
tREM
TIMIN G
INPUT
ASYN CHRONOUS
CONTROL
SYN CHRONOUS
CONTROL
tSU
tH
tSU
tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LOW -H IGH-LOW
PULSE
HIGH -LOW -HIGH
PULSE
VT
tW
SAME PHASE
INPUT TRAN SITION
OPPOSITE PH ASE
INPUT TRAN SITION
0V
0V
VOH
VOL
tPLH
tPHL
tPHL
tPLH
OUTPUT
VT
VIH
VT
VT
VIH
VT
CONTROL
INPUT
tPLZ
0V
OUTPUT
NORMALLY
LOW
tPZH
0V
SW ITCH
CLO SED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SW ITCH
OP EN
tPHZ
0V
VLZ
VOH
VT
VT
tPZL
VLOAD/2
VLOAD/2
VIH
VT
VOL
VHZ
ALVC Link
ALVC Link
ALVC Link
ALVC Link
ALVC Link
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Test
Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High
GND
All Other tests
Open
ALVC Link
Symbol
VCC(1)= 3.3V ±0.3V
VCC(1) = 2.7V
VCC(2)= 2.5V ±0.2V
Unit
VLOAD
66
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
VCC / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
ALVC Link
NOTES:
1. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
OUTPUT SKEW - TSK (x)
PULSE WIDTH


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