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DAC701KH データシート(PDF) 8 Page - Burr-Brown (TI) |
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DAC701KH データシート(HTML) 8 Page - Burr-Brown (TI) |
8 / 12 page 8 ® DAC701, 702, 703 In many applications it is impractical to sense the output voltage at the output pin. Sensing the output voltage at the system ground point is permissible with the DAC700 family because the D/A converter is designed to have a constant return current of approximately 2mA flowing from Com- mon. The variation in this current is under 20 µA (with changing input codes), therefore R4 can be as large as 3Ω without adversely affecting the linearity of the D/A con- verter. The voltage drop across R4 (R4 x 2mA) appears as a zero error and can be removed with the zero calibration adjustment. This alternate sensing point (the system ground point) is shown in Figures 6, 7, and 8. Figures 7 and 8 show two methods of connecting the current output models (DAC702) with external precision output op amps. By sensing the output voltage at the load resistor (ie, by connecting RF to the output of A1 at RL), the effect of R1 and R2 is greatly reduced. R1 will cause a gain error but is independent of the value of RL and can be eliminated by initial calibration adjustments. The effect of R2 is negligible because it is inside the feedback loop of the output op amp and is therefore greatly reduced by the loop gain. Zero Adjustment For unipolar (CSB) configurations, apply the digital input code that produces zero voltage or zero current output and adjust the zero potentiometer for zero output. For bipolar (COB, CTC) configurations, apply the digital input code that produces zero output voltage or current. See Table II for corresponding codes and the Connection Dia- gram for zero adjustment circuit connections. Zero calibra- tion should be made before gain calibration. Gain Adjustment Apply the digital input that gives the maximum positive output voltage. Adjust the gain potentiometer for this posi- tive full scale voltage. See Table II for positive full scale voltages and the Connection Diagram for gain adjustment circuit connections. INSTALLATION CONSIDERATIONS This D/A converter family is laser-trimmed to 14-bit linear- ity. The design of the device makes the 16-bit resolution available. If 16-bit resolution is not required, bit 15 and bit 16 should be connected to VDD through a single 1kΩ resistor. Due to the extremely high resolution and linearity of the D/A converter, system design problems such as grounding and contact resistance become very important. For a 16-bit converter with a 10V full-scale range, 1LSB is 153 µV. With a load current of 5mA, series wiring and connector resis- tance of only 30m Ω will cause the output to be in error by 1LSB. To understand what this means in terms of a system layout, the resistance of #23 wire is about 0.021 Ω/ft. Ne- glecting contact resistance, less than 18 inches of wire will produce a 1LSB error in the analog output voltage! In Figures 6, 7, and 8, lead and contact resistances are represented by R1 through R5. As long as the load resistance R L is constant, R2 simply introduces a gain error and can be removed during initial calibration. R3 is part of RL, if the output voltage is sensed at Common, and therefore intro- duces no error. If RL is variable, then R2 should be less than R L MIN/2 16 to reduce voltage drops due to wiring to less than 1LSB. For example, if RL MIN is 5kΩ, then R2 should be less than 0.08 Ω. R L should be located as close as possible to the D/A converter for optimum performance. The effect of R4 is negligible. FIGURE 6. Output Circuit for Voltage Models. A 1 R DAC 4k Ω DAC701 5k Ω R B Common V OUT R 2 * R L R 3 Sense Output +5VDC Supply ±15VDC Supply +V COM –V System Ground Point +V COM Alternate Ground Sense Connection R 4 To +V CC To –V CC To V DD 1µF 1µF 1µF * R = 2k (DAC701 and DAC703) B Ω R F |
同様の部品番号 - DAC701KH |
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同様の説明 - DAC701KH |
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