データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

GS816018CGT-333IT データシート(PDF) 1 Page - GSI Technology

部品番号 GS816018CGT-333IT
部品情報  1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
Download  22 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS816018CGT-333IT データシート(HTML) 1 Page - GSI Technology

  GS816018CGT-333IT Datasheet HTML 1Page - GSI Technology GS816018CGT-333IT Datasheet HTML 2Page - GSI Technology GS816018CGT-333IT Datasheet HTML 3Page - GSI Technology GS816018CGT-333IT Datasheet HTML 4Page - GSI Technology GS816018CGT-333IT Datasheet HTML 5Page - GSI Technology GS816018CGT-333IT Datasheet HTML 6Page - GSI Technology GS816018CGT-333IT Datasheet HTML 7Page - GSI Technology GS816018CGT-333IT Datasheet HTML 8Page - GSI Technology GS816018CGT-333IT Datasheet HTML 9Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 22 page
background image
GS816018/36CT-333/300/250
1M x 18 and 512K x 36
18Mb Sync Burst SRAMs
333 MHz–250 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
Rev: 1.00 9/2004
1/22
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS816018/36CT is an 18,874,368-bit (16,777,216-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS816018/36CT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-333
-300
-250
Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
3.0
2.5
3.3
2.5
4.0
ns
ns
Curr (x18)
Curr (x32/x36)
375
435
335
390
280
330
mA
mA
Flow Through
2-1-1-1
tKQ
tCycle
4.5
4.5
5.0
5.0
5.5
5.5
ns
ns
Curr (x18)
Curr (x32/x36)
260
300
230
270
210
240
mA
mA


同様の部品番号 - GS816018CGT-333IT

メーカー部品番号データシート部品情報
logo
GSI Technology
GS816018 GSI-GS816018 Datasheet
810Kb / 28P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BGT-150 GSI-GS816018BGT-150 Datasheet
925Kb / 24P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BGT-150I GSI-GS816018BGT-150I Datasheet
925Kb / 24P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BGT-150IV GSI-GS816018BGT-150IV Datasheet
927Kb / 23P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BGT-150V GSI-GS816018BGT-150V Datasheet
927Kb / 23P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
More results

同様の説明 - GS816018CGT-333IT

メーカー部品番号データシート部品情報
logo
GSI Technology
GS8161V18CD GSI-GS8161V18CD Datasheet
776Kb / 28P
   1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V18CT GSI-GS8160V18CT Datasheet
558Kb / 21P
   1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160E18T GSI-GS8160E18T Datasheet
622Kb / 25P
   1M x 18, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BT GSI-GS8161E18BT Datasheet
1Mb / 35P
   1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BT-V GSI-GS8161E18BT-V Datasheet
1Mb / 35P
   1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS816118C GSI-GS816118C Datasheet
769Kb / 29P
   1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
GS8160V18AT GSI-GS8160V18AT Datasheet
489Kb / 24P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018DGT-250I GSI-GS816018DGT-250I Datasheet
255Kb / 25P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BT GSI-GS816018BT Datasheet
925Kb / 24P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160F18T GSI-GS8160F18T Datasheet
544Kb / 22P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com