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SN74GTLPH16927GR データシート(PDF) 1 Page - Texas Instruments

部品番号 SN74GTLPH16927GR
部品情報  18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

SN74GTLPH16927GR データシート(HTML) 1 Page - Texas Instruments

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SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
 Family
D TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D GTLP Buffered SYSCLK Signal (SSCLK) for
Source-Synchronous Applications
D LVTTL Interfaces Are 5-V Tolerant
D Medium-Drive GTLP Outputs (50 mA)
D LVTTL Outputs (–24 mA/24 mA)
D GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
D Bus Hold on A-Port Data Inputs
D Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
The SN74GTLPH16927 is a medium-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer.
Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous
and clock-synchronous applications. Source-synchronous applications require the skew between the clock
output and data output to be minimized for optimum maximum-frequency system performance. In order to
reduce this skew, a flexible setup-time adjustment (FSTA) feature is incorporated into the device that sets a
predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the
device.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74GTLPH16927GR
GTLPH16927
–40
°C to 85°C
TVSOP – DGV
Tape and reel
SN74GTLPH16927VR
GL927
VFBGA – GQL
Tape and reel
SN74GTLPH16927KR
GL927
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
DGG OR DGV PACKAGE
(TOP VIEW)
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DIR
OE
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLKOUT
CKOE
FSTA
BIAS VCC
B1
GND
B2
B3
VREF
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
CMS
B16
B17
GND
B18
SSCLK
SYSCLK
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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