TPS71918-15DRVT datasheet(10/15 Pages) TI

部品番号	TPS71918-15DRVT

部品情報	Dual, 200mA Output, Low Noise, High PSRR Low-Dropout Linear Regulators in 2mm x 2mm SON Package

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Transient Response

Under-Voltage Lock-Out (UVLO)

Power Dissipation

Minimum Load

THERMAL INFORMATION

Thermal Protection

P

=(V

V

)xI

-

D

IN

OUT

(1)

Package Mounting

TPS718xx

TPS719xx

SBVS088A – FEBRUARY 2007 – REVISED MARCH 2007

As with any linear regulator, PSRR and transient

Any tendency to activate the thermal protection

response are degraded as (VIN – VOUT) approaches

circuit indicates excessive power dissipation or an

dropout. This effect is shown in Figure 13 and

inadequate heatsink. For reliable operation, junction

Figure 14 in the Typical Characteristics section.

temperature should be limited to +125

°C maximum.

To estimate the margin of safety in a complete

design (including heatsink), increase the ambient

temperature until the thermal protection is triggered;

As with any regulator, increasing the size of the

use worst-case loads and signal conditions. For good

output

capacitor

will

reduce

over/undershoot

reliability, thermal protection should trigger at least

magnitude but increase duration of the transient

+35

°C above the maximum expected ambient

response.

condition

of

your

particular

application.

This

configuration

produces

a

worst-case

junction

temperature of +125

°C at the highest expected

ambient temperature and worst-case load.

The TPS718xx/TPS719xx utilize an under-voltage

lock-out circuit to keep the output shut off until

The

internal

protection

circuitry

of

the

internal circuitry is operating properly. The UVLO

TPS718xx/TPS719xx has been designed to protect

circuit has a de-glitch feature so that it typically

against overload conditions. It was not intended to

ignores undershoot transients on the input if they are

replace proper heatsinking. Continuously running the

less than 50

µs duration. On the TPS719xx, the

TPS718xx/TPS719xx

into

thermal

shutdown

active pulldown discharges VOUT when the device is

degrades device reliability.

in UVLO off condition. However, the input voltage

needs to be greater than 0.8V for active pulldown to

work.

The ability to remove heat from the die is different for

each

package

type,

presenting

different

considerations in the printed circuit board (PCB)

The TPS718xx/TPS719xx are stable with no output

layout. The PCB area around the device that is free

load. Traditional PMOS LDO regulators suffer from

of other components moves the heat from the device

lower loop gain at very light output loads. The

to the ambient air. Performance data for JEDEC low-

TPS718xx/TPS719xx

employ

an

innovative,

and high-K boards are given in the Dissipation

low-current mode circuit under very light or no-load

Ratings table. Using heavier copper increases the

conditions, resulting in improved output voltage

effectiveness in removing heat from the device. The

regulation performance down to zero output current.

addition of plated through-holes to heat-dissipating

layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load

conditions. Power dissipation (PD) is equal to the

product of the output current times the voltage drop

Thermal protection disables the output when the

across the output pass element (VIN to VOUT), as

junction temperature rises to approximately +160

°C,

shown in Equation 1:

allowing the device to cool. When the junction

temperature cools to approximately +140

°C the

output circuitry is again enabled. Depending on

power dissipation, thermal resistance, and ambient

Solder

pad

footprint

recommendations

for

the

temperature, the thermal protection circuit may cycle

TPS718xx/TPS719xxx are available from the Texas

on and off. This cycling limits the dissipation of the

Instruments web site at www.ti.com.

regulator,

protecting

it

from

damage

due

to

overheating.

10

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