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MC10H161FN データシート(PDF) 1 Page - ON Semiconductor

部品番号 MC10H161FN
部品情報  Binary to 1-8 Decoder
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC10H161FN データシート(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 6
1
Publication Order Number:
MC10H161/D
MC10H161
Binary to 1-8 Decoder
(Low)
The MC10H161 provides parallel decoding of a three bit binary
word to one of eight lines. The MC10H161 is useful in high–speed
multiplexer/demultiplexer applications.
The MC10H161 is designed to decode a three bit input word to one
of eight output lines. The MC10H161 output will be low when
selected while all other output are high. The enable inputs, when either
or both are high, force all outputs high.
The MC10H161 is a true parallel decoder. This eliminates unequal
parallel path delay times found in other decoder designs. These
devices are ideally suited for multiplexer/demultiplexer applications.
Propagation Delay, 1.0 ns Typical
Power Dissipation, 315 mW Typical (same as MECL 10K)
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K–Compatible
LOGIC DIAGRAM
DIP PIN ASSIGNMENT
VCC1
E0
Q3
Q2
Q1
Q0
A
VEE
VCC2
E1
C
Q4
Q5
Q6
Q7
B
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCC1 = Pin 1
VCC2 = Pin 16
VEE = Pin 8
E02
E115
A7
B9
C14
6Q0
5Q1
4Q2
3Q3
13 Q4
12 Q5
11 Q6
10 Q7
H
H
H
H
L
H
H
H
H
H
L
L
L
L
L
L
L
L
X
H
TRUTH TABLE
ENABLE
INPUTS
INPUTS
OUTPUTS
L
L
L
L
L
L
L
L
H
X
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
X
X
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
Q4
E0
E1
C
B
A Q0 Q1 Q2 Q3
Q5 Q6 Q7
Pin assignment is for Dual–in–Line
Package. For PLCC pin assignment, see
the Pin Conversion Tables on page 18 of
the ON Semiconductor MECL Data
Book (DL122/D).
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10H161L
CDIP–16
25 Units/Rail
MC10H161P
PDIP–16
25 Units/Rail
MC10H161FN
PLCC–20
46 Units/Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10H161L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10H161
AWLYYWW
1
1
16
MC10H161P
AWLYYWW


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