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TPA0252PWP データシート(PDF) 3 Page - Texas Instruments |
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TPA0252PWP データシート(HTML) 3 Page - Texas Instruments |
3 / 32 page www.ti.com ABSOLUTE MAXIMUM RATINGS TPA0252 SLOS288B – JUNE 2000 – REVISED SEPTEMBER 2004 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. BYPASS 7 Tap to voltage divider for internal mid-supply bias generator If a 47-nF capacitor is attached, the TPA0252 generates an internal clock. An external clock can override CLK 6 I the internal clock input to this terminal. A momentary pulse on this terminal decreases the volume level by 2 dB. Holding the terminal low for a DOWN 5 I period of time steps the amplifier through the volume levels at a rate determined by the capacitor on the CLK terminal. GND 12, 24 I Ground connection for circuitry. Connected to thermal pad Input MUX control. When terminal is high, the LHPIN and RHPIN inputs are selected. When terminal is HP/LINE 14 I low, LLINEIN and RLINEIN inputs are selected. LHPIN 19 I Left-channel headphone input, selected when HP/LINE is held high LIN 21 I Common left input for fully differential input. AC ground for single-ended inputs LLINEIN 20 I Left-channel line negative input, selected when HP/LINE is held low LOUT+ 23 O Left-channel positive output in BTL mode and positive in SE mode LOUT– 1 O Left-channel negative output in BTL mode and high impedance in SE mode The input for PC beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave is input to PC-BEEP 10 I PC-BEEP. PVDD 3, 8 I Power supply for output stage RHPIN 17 I Right channel headphone input, selected when HP/LINE is held high RIN 15 I Common right input for fully differential input. AC ground for single-ended inputs RLINEIN 16 I Right-channel line input, selected when HP/LINE is held low ROUT+ 13 O Right-channel positive output in BTL mode and positive in SE mode ROUT– 11 O Right-channel negative output in BTL mode and high impedance in SE mode Input and output MUX control. When this terminal is held high SE outputs are selected. When this SE/BTL 22 I terminal is held low BTL outputs are selected. When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdown SHUTDOWN 2 I mode. A momentary pulse on this terminal increases the volume level by 2 dB. Holding the terminal low for a UP 4 I period of time steps the amplifier through the volume levels at a rate determined by the capacitor on the CLK terminal. Volume control memory supply. Connect to system auxiliary that stays active when device is powered VAUX 9 I down. VDD 18 I Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance. Thermal Pad Connect to ground. Must be soldered down in all applications to properly secure device on PC board. over operating free-air temperature range (unless otherwise noted)(1) Supply voltage, VDD 6 V Input voltage, VI -0.3 V to VDD +0.3 V Continuous total power dissipation internally limited (see Dissipation Rating Table) Operating free-air temperature range, TA -40 °C to 85°C Operating junction temperature range, TJ -40 °C to 150°C Storage temperature range, Tstg -65 °C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C (1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3 |
同様の部品番号 - TPA0252PWP |
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同様の説明 - TPA0252PWP |
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