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TLC1551IDWR データシート(PDF) 1 Page - Texas Instruments |
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TLC1551IDWR データシート(HTML) 1 Page - Texas Instruments |
1 / 16 page TLC1550I, TLC1550M, TLC1551I 10BIT ANALOGTODIGITAL CONVERTERS WITH PARALLEL OUTPUTS SLAS043G − MAY 1991 − REVISED NOVEMBER 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Power Dissipation . . . 40 mW Max D Advanced LinEPIC Single-Poly Process Provides Close Capacitor Matching for Better Accuracy D Fast Parallel Processing for DSP and µP Interface D Either External or Internal Clock Can Be Used D Conversion Time ...6 µs D Total Unadjusted Error . . . ±1 LSB Max D CMOS Technology description The TLC1550x and TLC1551 are data acquisition analog-to-digital converters (ADCs) using a 10-bit, switched-capacitor, successive-approximation net- work. A high-speed, 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor ( µP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). Separate power terminals for the analog and digital portions minimize noise pickup in the supply leads. Additionally, the digital power is divided into two parts to separate the lower current logic from the higher current bus drivers. An external clock can be applied to CLKIN to override the internal system clock if desired. The TLC1550I and TLC1551I are characterized for operation from − 40 °C to 85°C. The TLC1550M is characterized over the full military range of − 55 °C to 125 °C. AVAILABLE OPTIONS PACKAGE TA CERAMIC CHIP CARRIER (FK) PLASTIC CHIP CARRIER (FN) CERAMIC DIP (J) SOIC (DW) −40 °C to 85°C — TLC1550IFN TLC1551IFN — TLC1550IDW TLC1551IDW −55 °C to 125°C TLC1550MFK — TLC1550MJ — This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Copyright 2003, Texas Instruments Incorporated On products compliant to MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinEPIC is a trademark of Texas Instruments. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF+ REF − ANLG GND AIN ANLG VDD DGTL GND1 DGTL GND2 DGTL VDD1 DGTL VDD2 EOC D0 D1 RD WR CLKIN CS D9 D8 D7 D6 D5 D4 D3 D2 J† OR DW PACKAGE (TOP VIEW) 32 1 13 14 5 6 7 8 9 10 11 CS D9 D8 NC D7 D6 D5 AIN ANLG VDD DGTL GND1 NC DGTL GND2 DGTL VDD1 DGTL VDD2 4 15 16 17 18 28 27 26 25 24 23 22 21 20 19 12 NC − No internal connection FK OR FN PACKAGE (TOP VIEW) † Refer to the mechanical data for the JW package. |
同様の部品番号 - TLC1551IDWR |
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同様の説明 - TLC1551IDWR |
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