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INPUT RESISTANCE

IN

Input

Signal

f=

1

2

Z C

p

i

i

(1)

TPA3120D2

SLOS507 – MARCH 2007

APPLICATION INFORMATION (continued)

For design purposes, the input network (discussed in the next section) should be designed assuming an input

impedance of 8 k

Ω, which is the absolute minimum input impedance of the TPA3120D2. At the higher gain

settings, the input impedance could increase as high as 72 k

Ω

Table 1. Gain Setting

INPUT IMPEDANCE

AMPLIFIER GAIN (dB)

(k

Ω)

GAIN1

GAIN0

TYPICAL

TYPICAL

0

0

20

10

0

1

26

15

1

0

32

30

1

1

36

60

Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 10 k

Ω± 20%, to

the largest value, 60 k

Ω± 20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or

cutoff frequency may change when changing gain steps.

10

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