MC10E1651

http://onsemi.com

5

APPLICATIONS INFORMATION

The timing diagram (Figure 3.) is presented to illustrate

the MC10E1651’s compare and latch features. When the

signal on the LEN pin is at a logic high level, the device is

operating in the “compare mode,” and the signal on the input

to the negative going transition on LEN and held for a time,

operating in the “latch mode,” thus transitions on the input

do not appear at the output. The device continues to operate

in the “latch mode” until the latch is asserted once again.

Moreover, the LEN pulse must meet the minimum pulse

relationship. Note that the LEN waveform in Figure 3.

shows the LEN signal swinging around a reference labeled

LEN follow typical ECL 10KH logic levels because

the input is driven. As an example, if the threshold level is

set on one of the comparator inputs as 80 mV and the input

signal swing on the complementary input is from zero to

100 mV, the positive going overdrive would be 20 mV and

the negative going overdrive would be 80 mV. The result of

differing overdrive levels is that the devices have shorter

propagation delays with greater overdrive because the

threshold level is crossed sooner than the case of lower

overdrive levels. Typically, semiconductor manufactures

refer to the threshold voltage as the input offset voltage

(VOS) since the threshold voltage is the sum of the

externally supplied reference voltage and inherent device

offset voltage.

Figure 3. Input/Output Timing Diagram

Q

Q

V

LEN